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UCD3138ARGCR

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Texas Instruments Supervisor And Reset ICs, VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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UCD3138ARGCR

Texas Instruments · Supervisor And Reset ICs · VQFN-64-EP(9x9)

UCD3138ARGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AGND power_in Analog ground; the datasheet limits
2 AD13 passive 12-bit ADC channel 13, also connected to comparator E and the I-share DAC output.
3 AD12 passive 12-bit ADC channel 12 input.
4 AD10 passive 12-bit ADC channel 10 input.
5 AD07 passive 12-bit ADC channel 7, also connected to comparator F and to the reference DAC output for comparator G.
6 AD06 passive 12-bit ADC channel 6, also connected to comparator F and its DAC output.
7 AD04 passive 12-bit ADC channel 4, also connected to comparator D and its DAC output.
8 AD03 passive 12-bit ADC channel 3, also connected to comparators B and C.
9 V33DIO power_in Digital I/O 3.3 V supply; recommended operating range is 3 V to 3.6 V (Section 5.3).
10 DGND power_in Digital ground; the datasheet limits
11 RESET input Active-low device reset input.
12 ADC_EXT_TRIG input External trigger input for ADC conversions; alternate functions are TCAP, SYNC and PWM0, and the pin can be used as a GPIO.
13 SCI_RX0 bidirectional SCI (UART 0) receive; the pin can be used as a GPIO when the peripheral is not in use.
14 SCI_TX0 bidirectional SCI (UART 0) transmit; the pin can be used as a GPIO when the peripheral is not in use.
15 PMBUS_CLK bidirectional PMBus clock, open-drain; alternate function is SCI_TX0 and the pin can be used as a GPIO.
16 PMBUS_DATA bidirectional PMBus data, open-drain; alternate function is SCI_RX0 and the pin can be used as a GPIO.
17 DPWM0A bidirectional High-resolution DPWM channel 0A output (250 ps resolution); the pin can be used as a GPIO.
18 DPWM0B bidirectional High-resolution DPWM channel 0B output (250 ps resolution); the pin can be used as a GPIO.
19 DPWM1A bidirectional High-resolution DPWM channel 1A output (250 ps resolution); the pin can be used as a GPIO.
20 DPWM1B bidirectional High-resolution DPWM channel 1B output (250 ps resolution); the pin can be used as a GPIO.
21 DPWM2A bidirectional High-resolution DPWM channel 2A output (250 ps resolution); the pin can be used as a GPIO.
22 DPWM2B bidirectional High-resolution DPWM channel 2B output (250 ps resolution); the pin can be used as a GPIO.
23 DPWM3A bidirectional High-resolution DPWM channel 3A output (250 ps resolution); the pin can be used as a GPIO.
24 DPWM3B bidirectional High-resolution DPWM channel 3B output (250 ps resolution); the pin can be used as a GPIO.
25 DGND power_in Digital ground; the datasheet limits
26 SYNC bidirectional DPWM synchronization pin; alternate functions are TCAP, ADC_EXT_TRIG, PWM0 and DTC1, and the pin can be used as a GPIO.
27 PMBUS_ALERT bidirectional PMBus alert, open-drain; the pin can be used as a GPIO.
28 PMBUS_CTRL bidirectional PMBus control, open-drain; the pin can be used as a GPIO.
29 SCI_TX1 bidirectional SCI (UART 1) transmit; alternate function is PMBUS_ALERT and the pin can be used as a GPIO.
30 SCI_RX1 bidirectional SCI (UART 1) receive; alternate function is PMBUS_CTRL and the pin can be used as a GPIO.
31 PWM0 bidirectional General-purpose PWM output 0; the pin can be used as a GPIO.
32 PWM1 bidirectional General-purpose PWM output 1; the pin can be used as a GPIO.
33 DGND power_in Digital ground; the datasheet limits
34 INT_EXT input External interrupt input; the pin can be used as a GPIO.
35 FAULT0 input External fault input 0; the pin can be used as a GPIO.
36 FAULT1 input External fault input 1; the pin can be used as a GPIO.
37 TCK input JTAG TCK; alternate functions are TCAP, SYNC, PWM0 and DTC0, and the pin can be used as a GPIO.
38 TDO output JTAG TDO; alternate functions are SCI_TX0, PMBUS_ALERT, FAULT0 and DTC1, and the pin can be used as a GPIO.
39 TDI input JTAG TDI; alternate functions are SCI_RX0, PMBUS_CTRL, FAULT1 and DTC0, and the pin can be used as a GPIO.
40 TMS input JTAG TMS; the pin can be used as a GPIO.
41 TCAP input Timer capture input; the pin can be used as a GPIO.
42 FAULT2 input External fault input 2; the pin can be used as a GPIO.
43 FAULT3 input External fault input 3; the pin can be used as a GPIO.
44 DGND power_in Digital ground; the datasheet limits
45 V33DIO power_in Digital I/O 3.3 V supply; recommended operating range is 3 V to 3.6 V (Section 5.3).
46 BP18 power_out 1.8 V bypass pin for the internal 1.8 V regulator; recommended voltage is 1.6 V to 2 V (Section 5.3).
47 V33D power_in Digital 3.3 V core supply; recommended operating range is 3 V to 3.6 V (Section 5.3).
48 AGND power_in Substrate analog ground; the datasheet limits
49 AGND power_in Analog ground; the datasheet limits
50 EAP0 passive Channel 0 differential analog voltage positive input to the EADC.
51 EAN0 passive Channel 0 differential analog voltage negative input to the EADC.
52 EAP1 passive Channel 1 differential analog voltage positive input to the EADC.
53 EAN1 passive Channel 1 differential analog voltage negative input to the EADC.
54 EAP2 passive Channel 2 differential analog voltage positive input to the EADC; recommended for peak current mode control.
55 EAN2 passive Channel 2 differential analog voltage negative input to the EADC.
56 AGND power_in Analog ground; the datasheet limits
57 V33A power_in Analog 3.3 V supply; recommended operating range is 3 V to 3.6 V (Section 5.3).
58 AD00 passive 12-bit ADC channel 0, connected to a current source (used for PMBus address detection).
59 AD01 passive 12-bit ADC channel 1, connected to a current source (used for PMBus address detection).
60 AD02 passive 12-bit ADC channel 2, connected to comparator A and the I-share function.
61 AD05 passive 12-bit ADC channel 5 input.
62 AD08 passive 12-bit ADC channel 8 input.
63 AD09 passive 12-bit ADC channel 9 input.
64 AD11 passive 12-bit ADC channel 11 input.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-64-EP(9x9)
Category Power Management (PMIC)
Pins 65

CAD (KiCad official)

  • Symbol: UCD3138ARGCR
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: ucd3138argcr-etched.step / ucd3138argcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucd3138argcr.step / ucd3138argcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (85 pp, sha256 d8c76afb06ae469a, retrieved 2026-10-12, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF