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UCD3138064ARGCR

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Texas Instruments Supervisor And Reset ICs, VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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UCD3138064ARGCR

Texas Instruments · Supervisor And Reset ICs · VQFN-64-EP(9x9)

UCD3138064ARGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AGND power_in Analog ground.
2 AD13 input 12-bit ADC channel 13, also connected to comparator E and the I-share DAC output.
3 AD12 input 12-bit ADC channel 12.
4 AD10 input 12-bit ADC channel 10.
5 AD07 input 12-bit ADC channel 7, connected to comparator F and the reference to comparator G, with a DAC output alternate assignment.
6 AD06 input 12-bit ADC channel 6, connected to comparator F, with a DAC output alternate assignment.
7 AD04 input 12-bit ADC channel 4, connected to comparator D, with a DAC output alternate assignment.
8 AD03 input 12-bit ADC channel 3, connected to comparators B and C.
9 V33DIO power_in Digital I/O 3.3 V core supply, connected internally to V33D; recommended operating range 3.0 V to 3.6 V.
10 DGND power_in Digital ground.
11 RESET input Device reset input, active low.
12 ADC_EXT bidirectional ADC conversion external trigger input; alternate assignments TCAP, SYNC, PWM0; configurable as GPIO.
13 SCI_RX0 bidirectional SCI receive 0; alternate assignment DTC0; configurable as GPIO.
14 SCI_TX0 bidirectional SCI transmit 0; alternate assignment DTC1; configurable as GPIO.
15 PMBUS_CLK bidirectional PMBus clock, open drain; alternate assignment SCI TX 0; configurable as GPIO.
16 PMBUS_DATA bidirectional PMBus data, open drain; alternate assignment SCI RX 0; configurable as GPIO.
17 DPWM0A output DPWM 0A high-resolution PWM output (250 ps pulse width resolution); configurable as GPIO.
18 DPWM0B output DPWM 0B high-resolution PWM output (250 ps pulse width resolution); configurable as GPIO.
19 DPWM1A output DPWM 1A high-resolution PWM output (250 ps pulse width resolution); configurable as GPIO.
20 DPWM1B output DPWM 1B high-resolution PWM output (250 ps pulse width resolution); configurable as GPIO.
21 DPWM2A output DPWM 2A high-resolution PWM output (250 ps pulse width resolution); configurable as GPIO.
22 DPWM2B output DPWM 2B high-resolution PWM output (250 ps pulse width resolution); configurable as GPIO.
23 DPWM3A output DPWM 3A high-resolution PWM output (250 ps pulse width resolution); configurable as GPIO.
24 DPWM3B output DPWM 3B high-resolution PWM output (250 ps pulse width resolution); configurable as GPIO.
25 DGND power_in Digital ground.
26 SYNC bidirectional DPWM synchronize pin; alternate assignments TCAP, ADC_EXT_TRIG, PWM0, DTC1; configurable as GPIO.
27 PMBUS_ALERT bidirectional PMBus alert, open drain; configurable as GPIO.
28 PMBUS_CTRL bidirectional PMBus control, open drain; configurable as GPIO.
29 SCI_TX1 bidirectional SCI transmit 1; alternate assignment PMBUS_ALERT; configurable as GPIO.
30 SCI_RX1 bidirectional SCI receive 1; alternate assignment PMBUS_CTRL; configurable as GPIO.
31 PWM0 bidirectional General-purpose PWM 0; configurable as GPIO.
32 PWM1 bidirectional General-purpose PWM 1; configurable as GPIO.
33 DGND power_in Digital ground.
34 INT_EXT bidirectional External interrupt; configurable as GPIO.
35 FAULT0 bidirectional External fault input 0; alternate assignments SPI_CS, I2C_DATA; configurable as GPIO.
36 FAULT1 bidirectional External fault input 1; alternate assignments SPI_CLK, I2C_CLK; configurable as GPIO.
37 TCK input JTAG TCK, for manufacturer test only; the datasheet recommends Fusion Digital Power based debug tools instead of JTAG. Alternate assignments TCAP, SYNC, PWM0, DTC0.
38 TDO output JTAG TDO, for manufacturer test only; the datasheet recommends Fusion Digital Power based debug tools instead of JTAG. Alternate assignments SCI_TX0, PMBUS_ALERT, FAULT0, SPI_MOSI, DTC1.
39 TDI input JTAG TDI, for manufacturer test only; the datasheet recommends Fusion Digital Power based debug tools instead of JTAG. Alternate assignments SCI_RX0, PMBUS_CTRL, FAULT1, SPI_MISO, DTC0.
40 TMS input JTAG TMS, for manufacturer test only; the datasheet recommends Fusion Digital Power based debug tools instead of JTAG.
41 TCAP input Timer capture input; configurable as GPIO.
42 FAULT2 input External fault input 2; configurable as GPIO.
43 FAULT3 input External fault input 3.
44 DGND power_in Digital ground.
45 V33DIO power_in Digital I/O 3.3 V core supply, connected internally to V33D; recommended operating range 3.0 V to 3.6 V.
46 BP18 passive 1.8 V bypass pin; recommended 1.8-V digital power range 1.6 V to 2 V.
47 V33D power_in Digital 3.3 V core supply; V33DIO is connected internally to V33D; recommended operating range 3.0 V to 3.6 V.
48 AGND power_in Substrate analog ground.
49 AGND power_in Analog ground.
50 EAP0 input Channel 0 differential analog voltage, positive input to the EADC.
51 EAN0 input Channel 0 differential analog voltage, negative input to the EADC.
52 EAP1 input Channel 1 differential analog voltage, positive input to the EADC.
53 EAN1 input Channel 1 differential analog voltage, negative input to the EADC.
54 EAP2 input Channel 2 differential analog voltage, positive input to the EADC.
55 EAN2 input Channel 2 differential analog voltage, negative input to the EADC.
56 AGND power_in Analog ground.
57 V33A power_in Analog 3.3 V supply; recommended operating range 3.0 V to 3.6 V.
58 AD00 input 12-bit ADC channel 0, connected to a current source (used for PMBus address decoding).
59 AD01 input 12-bit ADC channel 1, connected to a current source (used for PMBus address decoding).
60 AD02 input 12-bit ADC channel 2, connected to comparator A and the I-share function.
61 AD05 input 12-bit ADC channel 5.
62 AD08 input 12-bit ADC channel 8.
63 AD09 input 12-bit ADC channel 9.
64 AD11 input 12-bit ADC channel 11.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-64-EP(9x9)
Category Power Management (PMIC)
Pins 65

CAD (KiCad official)

  • Symbol: UCD3138064ARGCR
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: ucd3138064argcr-etched.step / ucd3138064argcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucd3138064argcr.step / ucd3138064argcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (88 pp, sha256 127ff2ee4354f907, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF