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docs ucc5320scdwvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers ucc5320scdwvr: viewers · Ray 1mo ago
package.json ucc5320scdwvr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
page.json ucc5320scdwvr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
README.md Initial commit: component/ucc5320scdwvr · Ray 1mo ago
ucc5320scdwvr-etched.fit.json ucc5320scdwvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ucc5320scdwvr-etched.glb ucc5320scdwvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ucc5320scdwvr-etched.step ucc5320scdwvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ucc5320scdwvr.glb Publish 0.1.0 · Ray 1mo ago
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ucc5320scdwvr.step Publish 0.1.0 · Ray 1mo ago

UCC5320SCDWVR

Texas Instruments · Isolators - Gate Drivers · SOIC-8-300mil

UCC5320SCDWVR from Texas Instruments, in a SOIC-8-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC1 power_in Input supply voltage; connect a locally decoupled low-ESR or ESL capacitor to GND as close to the device as possible.
2 IN+ input Noninverting gate-drive voltage-control input with CMOS input threshold; pulled low internally if left open.
3 IN- input Inverting gate-drive voltage-control input with CMOS input threshold; pulled high internally if left open.
4 GND1 power_in Input ground; all signals on the input side are referenced to this ground.
5 VCC2 power_in Positive output supply rail; connect a locally decoupled low-ESR or ESL capacitor to VEE2 as close to the device as possible.
6 OUTH output Gate-drive pull-up output (split output version); drives IGBT or MOSFET gate high during turn-on.
7 OUTL output Gate-drive pull-down output (split output version); drives IGBT or MOSFET gate low during turn-off.
8 VEE2 power_in Negative output supply rail (GND for S version); connect a locally decoupled low-ESR or ESL capacitor as close to the device as possible.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8-300mil
Category Power Management (PMIC)
Pins 8

CAD (KiCad official)

  • Symbol: UCC5320SCDWVR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8-300mil (KiCad packages3D, STEP)
  • 3D model files: ucc5320scdwvr-etched.step / ucc5320scdwvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc5320scdwvr.step / ucc5320scdwvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (58 pp, sha256 c0b99000e2aeb8bc, retrieved 2026-09-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF