component
UCC38C43DR
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownUCC38C43DR
Texas Instruments · AC-DC Controllers And Regulators · SOIC-8
UCC38C43DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier output pin for compensation with internally current-limited design allowing external zero duty cycle command. |
| 2 | FB | input | Inverting input to error amplifier with 2.5V ± 1% internal reference on noninverting input for voltage-feedback loop control and stability. |
| 3 | CS | input | Current sense input pin with maximum amplitude of 1V (0.9V to 1.1V typical) as noninverting PWM comparator input for cycle-by-cycle overcurrent protection at 35ns delay. |
| 4 | RT/CT | bidirectional | Oscillator timing pin for programming switching frequency via external timing resistor to VREF and timing capacitor to GND. |
| 5 | GND | power_in | Ground return pin for output driver stage and logic level controller section. |
| 6 | OUT | output | Gate driver output stage capable of sourcing and sinking up to 1A peak current with 25ns typical rise time and 20ns typical fall time for direct MOSFET drive. |
| 7 | VDD | power_in | Analog controller bias input with 20V absolute maximum rating and 2.3mA to 3mA typical operating current requiring 0.1µF bypass capacitor to GND. |
| 8 | VREF | power_in | 5V reference voltage output (4.9V to 5.1V at 25°C with ±1% initial accuracy) for oscillator timing and internal bias current setting requiring 0.1µF ceramic bypass capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
UCC38C43DR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ucc38c43dr-etched.step/ucc38c43dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucc38c43dr.step/ucc38c43dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (60 pp, sha256
9fa55f996731c56b, retrieved 2026-09-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).