component
UCC38C42DR
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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UCC38C42DR
Texas Instruments · AC-DC Controllers And Regulators · SOIC-8
UCC38C42DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier output for compensation with internal current limit allowing zero duty cycle command by forcing pin to GND. |
| 2 | FB | input | Inverting input to error amplifier with 2.5V ± 1% noninverting reference for voltage-feedback loop control. |
| 3 | CS | input | Primary-side current sense input (noninverting to PWM comparator) compared against error amplifier output to terminate OUT switch conduction. |
| 4 | RT/CT | bidirectional | Oscillator set point pin; connect timing resistor (RRT) to VREF and timing capacitor (CCT) to GND to program switching frequency. |
| 5 | GND | power_in | Ground return pin for output driver stage and logic level controller section. |
| 6 | OUT | output | Gate driver output with ±1A peak current drive and rail-to-rail swing; actively held low when VDD below turn-on threshold. |
| 7 | VDD | power_in | Analog controller bias supply input (maximum 20V) requiring 0.1µF bypass capacitor directly to GND with minimal trace length. |
| 8 | VREF | power_out | 5V reference output with ±1% accuracy used to provide charging current through timing resistor; requires minimum 0.1µF ceramic bypass capacitor to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
UCC38C42DR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ucc38c42dr-etched.step/ucc38c42dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucc38c42dr.step/ucc38c42dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (60 pp, sha256
9fa55f996731c56b, retrieved 2026-10-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# UCC38C42DR
**Texas Instruments** · AC-DC Controllers And Regulators · SOIC-8
UCC38C42DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier output for compensation with internal current limit allowing zero duty cycle command by forcing pin to GND. |
| 2 | FB | input | Inverting input to error amplifier with 2.5V ± 1% noninverting reference for voltage-feedback loop control. |
| 3 | CS | input | Primary-side current sense input (noninverting to PWM comparator) compared against error amplifier output to terminate OUT switch conduction. |
| 4 | RT/CT | bidirectional | Oscillator set point pin; connect timing resistor (RRT) to VREF and timing capacitor (CCT) to GND to program switching frequency. |
| 5 | GND | power_in | Ground return pin for output driver stage and logic level controller section. |
| 6 | OUT | output | Gate driver output with ±1A peak current drive and rail-to-rail swing; actively held low when VDD below turn-on threshold. |
| 7 | VDD | power_in | Analog controller bias supply input (maximum 20V) requiring 0.1µF bypass capacitor directly to GND with minimal trace length. |
| 8 | VREF | power_out | 5V reference output with ±1% accuracy used to provide charging current through timing resistor; requires minimum 0.1µF ceramic bypass capacitor to GND. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `UCC38C42DR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ucc38c42dr-etched.step` / `ucc38c42dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ucc38c42dr.step` / `ucc38c42dr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/ucc38c42.pdf) (60 pp, sha256 `9fa55f996731c56b`, retrieved 2026-10-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ucc38c42dr-datasheet.pdf)