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UCC38C40DGKR
Public Made by Adomby adom
Texas Instruments DC-DC Controllers, VSSOP-8-0.65mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownUCC38C40DGKR
Texas Instruments · DC-DC Controllers · VSSOP-8-0.65mm
UCC38C40DGKR from Texas Instruments, in a VSSOP-8-0.65mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier output for loop compensation; the amplifier is internally current-limited, so forcing COMP to GND commands zero duty cycle. |
| 2 | FB | input | Inverting input of the error amplifier, with the noninverting reference internally trimmed to 2.5V ±1%. |
| 3 | CS | input | Primary-side current sense input to the PWM comparator that terminates OUT conduction, with a typical current-sense amplifier gain of 3 V/V. |
| 4 | RT/CT | bidirectional | Oscillator timing pin where a timing resistor RRT connected to VREF and a timing capacitor CCT connected to GND set the switching frequency. |
| 5 | GND | power_in | Ground return for the output driver stage and the logic-level controller section. |
| 6 | OUT | output | Totem-pole gate drive output intended to drive a MOSFET directly, sourcing and sinking up to 1A peak, and actively held low when VDD is below the turn-on threshold. |
| 7 | VDD | power_in | Analog controller bias supply input with an absolute maximum of 20V, requiring a 0.1µF ceramic bypass capacitor connected directly to GND. |
| 8 | VREF | power_out | 5V reference output with ±1% tolerance, requiring a minimum 0.1µF ceramic bypass to GND placed as close to the pin as possible. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-8-0.65mm |
| Category | Power Supply Chip |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage VDD | VDD | 20 | V | 5 | |||
| Input current | IVDD | 30 | mA | 5 | |||
| Output drive current (peak) | -1 | 1 | A | 5 | |||
| Output energy (capacitive load) | EOUT | 5 | µJ | 5 | |||
| Analog input voltage COMP, CS, FB, RT/CT | -0.3 | 6.3 | V | 5 | |||
| Output driver voltage | OUT | -0.3 | 20 | V | 5 | ||
| Reference voltage | VREF | 7 | V | 5 | |||
| Error amplifier output sink current | COMP | 10 | mA | 5 | |||
| Lead temperature (soldering, 10 s) | TLEAD | 300 | °C | 10 s soldering | 5 | ||
| Operating junction temperature | TJ | -55 | 150 | °C | 5 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| Input voltage VDD | VVDD | 18 | V | 6 | |||
| Output driver voltage | VOUT | 18 | V | 6 | |||
| Maximum continuous voltage from external circuitry | VREF | 5.5 | V | 6 | |||
| Average output driver current (source and sink) | IOUT | 200 | mA | 6 | |||
| Reference output current (source) | IOUT(VREF) | 20 | mA | 6 | |||
| Operating junction temperature (UCC38C4x) | TJ | 0 | 85 | °C | 6 | ||
| VREF voltage, initial accuracy | VREF | 4.9 | 5 | 5.1 | V | TJ = 25°C, IOUT = 1mA | 7 |
| Total output variation | VREF | 4.82 | 5.18 | V | See (2) | 7 | |
| Line regulation | 0.2 | 20 | mV | VVDD = 12V to 18V | 7 | ||
| Load regulation | 3 | 25 | mV | 1mA to 20mA | 7 | ||
| Temperature stability | 0.2 | 0.4 | mV/°C | See (2) | 7 | ||
| Long term stability | 5 | 25 | mV | 1000 hours, TJ = 125°C, see (2) | 7 | ||
| Output short circuit (source current) | IVREF | 30 | 45 | 55 | mA | 7 | |
| Initial accuracy | fOSC | 50.5 | 53 | 55 | kHz | TJ = 25°C, see (3) | 7 |
| Voltage stability | 0.2 | 1 | % | 12V ≤ VVDD ≤ 18V | 7 | ||
| Temperature stability (oscillator) | 1 | 2.5 | % | TJ(MIN) to TJ(MAX), see (2) | 7 | ||
| Discharge current | 7.7 | 8.4 | 9 | mA | TJ = 25°C, VRT/CT = 2V, see (4) | 7 | |
| Discharge current | 7.2 | 8.4 | 9.5 | mA | VRT/CT = 2V, see (4) | 7 | |
| Feedback input voltage, initial accuracy | VFB | 2.475 | 2.5 | 2.525 | V | VCOMP = 2.5V, TJ = 25°C | 7 |
| Feedback input voltage, total variation | VFB | 2.45 | 2.5 | 2.55 | V | VCOMP = 2.5V | 7 |
| Input bias current (source current) | IFB | 0.1 | 2 | µA | VFB = 5V | 7 | |
| Open-loop voltage gain | AVOL | 65 | 90 | dB | 2V ≤ VOUT ≤ 4V | 7 | |
| Unity gain bandwidth | 1 | 1.5 | MHz | See (2) | 7 | ||
| Output sink current | 2 | 14 | mA | VFB = 2.7V, VCOMP = 1.1V | 7 | ||
| Output source current | 0.5 | 1 | mA | VFB = 2.3V, VCOMP = 5V | 7 | ||
| Low-level COMP voltage | VOL | 0.1 | 1.1 | V | VFB = 2.7V, RCOMP = 15kΩ COMP to VREF | 7 | |
| Current sense gain | ACS | 2.85 | 3 | 3.15 | V/V | See (5) (6) | 8 |
| Maximum input signal | VCS | 0.9 | 1 | 1.1 | V | VFB < 2.4V | 8 |
| Input bias current (source current) | ICS | 0.1 | 2 | µA | 8 | ||
| CS to output delay | tD | 35 | 70 | ns | 8 | ||
| RDS(on) pulldown | VOUT(low) | 5.5 | 15 | Ω | ISINK = 200mA | 8 | |
| RDS(on) pullup | VOUT(high) | 10 | 25 | Ω | ISOURCE = 200mA | 8 | |
| Rise time | tRISE | 25 | 50 | ns | TJ = 25°C, COUT = 1nF | 8 | |
| Fall time | tFALL | 20 | 40 | ns | TJ = 25°C, COUT = 1nF | 8 | |
| Start threshold (UCCx8C40, UCCx8C41) | VDDON | 6.5 | 7 | 7.5 | V | 8 | |
| Minimum operating voltage (UCCx8C40, UCCx8C41) | VDDOFF | 6.1 | 6.6 | 7.1 | V | 8 | |
| Maximum duty cycle (UCCx8C40, UCCx8C42, UCCx8C43 row) | DMAX | 94 | 96 | % | VFB < 2.4 V | 8 | |
| Start-up current | ISTART-UP | 50 | 100 | µA | VVDD = VDDON – 0.5V | 8 | |
| Operating supply current | IVDD | 2.3 | 3 | mA | VFB = VCS = 0V | 8 | |
| Thermal resistance, junction-to-ambient (DGK) | RθJA | 176.4 | °C/W | DGK (VSSOP) package | 7 | ||
| Thermal resistance, junction-to-case (top) (DGK) | RθJC(top) | 67.3 | °C/W | DGK (VSSOP) package | 7 | ||
| Thermal resistance, junction-to-board (DGK) | RθJB | 98.1 | °C/W | DGK (VSSOP) package | 7 | ||
| Junction-to-top characterization parameter (DGK) | ψJT | 11.1 | °C/W | DGK (VSSOP) package | 7 | ||
| Junction-to-board characterization parameter (DGK) | ψJB | 91.5 | °C/W | DGK (VSSOP) package | 7 |
CAD (KiCad official)
- Symbol:
UCC38C40DGKR - Footprint:
Package_SO:VSSOP-8_2.3x2mm_P0.5mm - 3D model: VSSOP-8-0.65mm (KiCad packages3D, STEP)
- 3D model files:
ucc38c40dgkr-etched.step/ucc38c40dgkr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucc38c40dgkr.step/ucc38c40dgkr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (60 pp, sha256
9fa55f996731c56b, retrieved 2026-10-10, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).