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Ray Publish 0.1.0 b49027d 28d ago

UCC3810DW

Texas Instruments · AC-DC Controllers And Regulators · SOIC-16-300mil

UCC3810DW from Texas Instruments, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SYNC input Edge-triggered TTL-threshold logic input that synchronizes the oscillator to an external free-running oscillator and requires a pulse at least 10 ns wide; if unused it may be grounded, left open, or connected to REF.
2 CT output Oscillator timing capacitor node; the timing capacitor connects directly across CT and GND, with recommended values between 100 pF and 1 nF.
3 RT output Oscillator timing resistor node regulated to 1 V, setting the charging current at 10 V/RT, with recommended RT values between 10 kΩ and 470 kΩ.
4 FB1 input High-impedance inverting input of error amplifier 1, with FB input voltage of 2.50 V typical (2.44 V to 2.56 V) and input bias current of ±1 µA.
5 COMP1 output Low-impedance output of error amplifier 1, which sets the PWM 1 control level.
6 CS1 input Current-sense input to PWM comparator 1 with leading-edge blanking that disconnects CS from internal circuits for the first 55 ns of each PWM cycle, and a small R-C filter may be needed in noisy applications.
7 OUT1 output High-current push-pull output of PWM 1 intended to drive power MOSFET gates through a small series resistor (10 Ω is typical for most applications).
8 GND power_in Ground reference for the control circuits, which must be electrically connected to PWRGND while avoiding coupling of noise into GND.
9 PWRGND power_in Power ground for the high-current output stages, which must be electrically connected to GND.
10 OUT2 output High-current push-pull output of PWM 2 intended to drive power MOSFET gates through a small series resistor that limits current and damps ringing.
11 CS2 input Current-sense input to PWM comparator 2 with leading-edge blanking of the first 55 ns of each PWM cycle, and a small R-C filter may be needed in noisy applications.
12 COMP2 output Low-impedance output of error amplifier 2, which sets the PWM 2 control level.
13 FB2 input High-impedance inverting input of error amplifier 2, with FB input voltage of 2.50 V typical (2.44 V to 2.56 V) and input bias current of ±1 µA.
14 ENABLE2 input Logic input that disables PWM 2 when low, with no effect on PWM 1; it is internally pulled high, has TTL-compatible thresholds, and may be left floating.
15 REF output 5-V reference output that should be bypassed to GND with a ceramic capacitor of at least 0.01 µF for best performance, with output of 4.85 V to 5.10 V over the full temperature range and up to 5 mA load.
16 VCC power_in Power input supplying all functions including the output stages and precision reference, to be bypassed to PWRGND with a 0.1-µF ceramic capacitor; the absolute maximum is 11 V with supply current limited to 20 mA.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16-300mil
Category Power Management (PMIC)
Pins 16

CAD (KiCad official)

  • Symbol: UCC3810DW
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: ucc3810dw-etched.step / ucc3810dw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc3810dw.step / ucc3810dw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 b7a04f61c8240c01, retrieved 2026-10-12, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF