component
UCC38084PWR
Public Made by Adomby adom
Texas Instruments DC-DC Controllers, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ucc38084pwr: specified limits as data (metadata.characteristics, 42 rows from the datasheet)
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10d ago
UCC38084PWR
Texas Instruments · DC-DC Controllers · TSSOP-8
UCC38084PWR from Texas Instruments, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUTB | output | Alternating high-current push-pull output stage that drives a power MOSFET gate, rated for 500-mA peak source and 1-A peak sink current and switching at half the oscillator frequency. |
| 2 | GND | power_in | Reference ground and power ground for all functions; due to high currents and high-frequency operation, a low-impedance circuit board ground plane is highly recommended. |
| 3 | RT | input | Oscillator programming pin; an external resistor to GND sets the oscillator frequency, with a recommended timing resistor range of 25 kΩ to 698 kΩ and a nominal RT voltage of 1.5 V (1.2 V to 1.6 V). |
| 4 | CS | input | Current-sense input to the PWM comparator, cycle-by-cycle peak current comparator and overcurrent comparator; exceeding the overcurrent threshold (0.75 V typical) causes a soft-start cycle, and an internal MOSFET discharges the CS filter capacitor. |
| 5 | ISET | input | Current selection for slope compensation; a resistor RSET from ISET to GND programs the slope-compensation ramp, with IRAMP peak equal to 5 × ISET peak. |
| 6 | CTRL | input | Error voltage input to the PWM comparator, with an internal divider ratio of 0.45 to maintain a usable range with the minimum VDD of 4.1 V. |
| 7 | VDD | power_in | Power input connection with an absolute maximum supply voltage of 15 V (IDD < 10 mA); a 1-µF decoupling capacitor to GND is recommended. |
| 8 | OUTA | output | Alternating high-current push-pull output stage that drives a power MOSFET gate, rated for 500-mA peak source and 1-A peak sink current and switching at half the oscillator frequency. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-8 |
| Category | Power Supply Chip |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | 15 | V | IDD < 10 mA | 3 | ||
| Supply current | IDD | 20 | mA | 3 | |||
| Sink current (peak) OUTA | 1 | A | 3 | ||||
| Sink current (peak) OUTB | 1 | A | 3 | ||||
| Source current (peak) OUTA | -0.5 | A | 3 | ||||
| Source current (peak) OUTB | -0.5 | A | 3 | ||||
| Analog input CTRL voltage | -0.3 | V | Printed as -0.3 V to VDD +0.3 V; upper limit is an expression, not a number | 3 | |||
| Analog input CS voltage | -0.3 | 6 | V | Printed as -0.3 V to VDD +0.3 V, not to exceed 6 V | 3 | ||
| RSET minimum resistance | RSET | 5 | kΩ | Printed as >5 kΩ (minimum) | 3 | ||
| RT pin voltage (absolute range) | RT | -0.3 | 2 | V | -100 µA < IRT < 100 µA | 3 | |
| Power dissipation at TA = 25°C (PW package) | PD | 400 | mW | TA = 25°C | 3 | ||
| Junction operating temperature | TJ | -55 | 150 | °C | 3 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Lead temperature (soldering) | 300 | °C | Soldering 10 seconds | 3 | |||
| Operating free-air temperature (UCC3808x) | TA | 0 | 70 | °C | UCC38084PW (UCC3808x family) | 3 | |
| Start-up current | 120 | 200 | µA | VDD < UVLO start threshold voltage | 3 | ||
| Supply current | 1.5 | 2.5 | mA | CTRL = 0 V, CS = 0 V, See Note 1 | 3 | ||
| Start threshold voltage UCC38084/6 | 4.1 | 4.3 | 4.5 | V | See Note 1 | 3 | |
| Minimum operating voltage after start UCC38084/6 | 3.9 | 4.1 | 4.3 | V | 3 | ||
| Hysteresis voltage UCC38084/6 | 0.1 | 0.2 | 0.3 | V | 3 | ||
| Oscillator frequency | 2 x f(OUTA) | 180 | 200 | 220 | kHz | 3 | |
| Oscillator voltage amplitude | 1.4 | 1.5 | 1.6 | V | See Note 2 | 3 | |
| Oscillator fall time (dead time) | 110 | 220 | ns | 3 | |||
| RT pin voltage | RT | 1.2 | 1.5 | 1.6 | V | 3 | |
| Current sense gain | 1.9 | 2.2 | 2.5 | V/V | See Note 3 | 4 | |
| Maximum input signal voltage | 0.47 | 0.52 | 0.57 | V | CTRL = 5 V, See Note 4 | 4 | |
| CS to output delay time | 100 | 200 | ns | CTRL = 3.5 V, 0 mV ≤ CS ≤ 600 mV | 4 | ||
| Source current | -200 | nA | 4 | ||||
| Sink current | 3 | 7 | 12 | mA | CS = 0.5 V, RT = 2.0 V, See Note 5 | 4 | |
| Overcurrent threshold voltage | 0.7 | 0.75 | 0.8 | V | 4 | ||
| CTRL to CS offset voltage (25°C) | 0.55 | 0.7 | 0.9 | V | CS = 0 V, 25°C | 4 | |
| CTRL to CS offset voltage | 0.37 | 0.7 | 1.1 | V | CS = 0 V | 4 | |
| Maximum duty cycle | 48 | 49 | 50 | % | Measured at OUTA or OUTB, See Note 7 | 4 | |
| Minimum duty cycle | 0 | % | CTRL = 0 V | 4 | |||
| Low-level output voltage (OUTA or OUTB) | 0.5 | 1 | V | IOUT = 100 mA | 4 | ||
| High-level output voltage (OUTA or OUTB) | VDD − VOUT | 0.5 | 1 | V | IOUT = −50 mA, See Note 6 | 4 | |
| Output rise time | 25 | 60 | ns | CLOAD = 1 nF | 4 | ||
| Output fall time | 25 | 60 | ns | CLOAD = 1 nF | 4 | ||
| OUTA/OUTB soft-start interval time UCC38083/4 | 1.3 | 3.5 | 8.5 | ms | CTRL = 1.8 V, CS = 0 V, Duty cycle from 0 to full, See Note 8 | 4 | |
| Peak slope compensation ramp current IRAMP | IRAMP | 125 | 150 | 175 | µA | ISET, peak = 30 µA, Full duty cycle | 4 |
| Thermal resistance junction-to-case (PW) | θjc | 32 | °C/W | Note 2 (modeled data) | 2 | ||
| Thermal resistance junction-to-ambient (PW) | θja | 232 | 257 | °C/W | Modeled data (Note 2): lower value 3x3 inch board, higher value 1x1 inch ground plane | 2 |
CAD (KiCad official)
- Symbol:
UCC38084PWR - Footprint:
Package_SO:TSSOP-8_3x3mm_P0.65mm - 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files:
ucc38084pwr-etched.step/ucc38084pwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucc38084pwr.step/ucc38084pwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (28 pp, sha256
19bab60962d5c6f5, retrieved 2026-10-08, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# UCC38084PWR
**Texas Instruments** · DC-DC Controllers · TSSOP-8
UCC38084PWR from Texas Instruments, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUTB | output | Alternating high-current push-pull output stage that drives a power MOSFET gate, rated for 500-mA peak source and 1-A peak sink current and switching at half the oscillator frequency. |
| 2 | GND | power_in | Reference ground and power ground for all functions; due to high currents and high-frequency operation, a low-impedance circuit board ground plane is highly recommended. |
| 3 | RT | input | Oscillator programming pin; an external resistor to GND sets the oscillator frequency, with a recommended timing resistor range of 25 kΩ to 698 kΩ and a nominal RT voltage of 1.5 V (1.2 V to 1.6 V). |
| 4 | CS | input | Current-sense input to the PWM comparator, cycle-by-cycle peak current comparator and overcurrent comparator; exceeding the overcurrent threshold (0.75 V typical) causes a soft-start cycle, and an internal MOSFET discharges the CS filter capacitor. |
| 5 | ISET | input | Current selection for slope compensation; a resistor RSET from ISET to GND programs the slope-compensation ramp, with IRAMP peak equal to 5 × ISET peak. |
| 6 | CTRL | input | Error voltage input to the PWM comparator, with an internal divider ratio of 0.45 to maintain a usable range with the minimum VDD of 4.1 V. |
| 7 | VDD | power_in | Power input connection with an absolute maximum supply voltage of 15 V (IDD < 10 mA); a 1-µF decoupling capacitor to GND is recommended. |
| 8 | OUTA | output | Alternating high-current push-pull output stage that drives a power MOSFET gate, rated for 500-mA peak source and 1-A peak sink current and switching at half the oscillator frequency. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-8 |
| Category | Power Supply Chip |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | | | 15 | V | IDD < 10 mA | 3 |
| Supply current | IDD | | | 20 | mA | | 3 |
| Sink current (peak) OUTA | | | | 1 | A | | 3 |
| Sink current (peak) OUTB | | | | 1 | A | | 3 |
| Source current (peak) OUTA | | -0.5 | | | A | | 3 |
| Source current (peak) OUTB | | -0.5 | | | A | | 3 |
| Analog input CTRL voltage | | -0.3 | | | V | Printed as -0.3 V to VDD +0.3 V; upper limit is an expression, not a number | 3 |
| Analog input CS voltage | | -0.3 | | 6 | V | Printed as -0.3 V to VDD +0.3 V, not to exceed 6 V | 3 |
| RSET minimum resistance | RSET | 5 | | | kΩ | Printed as >5 kΩ (minimum) | 3 |
| RT pin voltage (absolute range) | RT | -0.3 | | 2 | V | -100 µA < IRT < 100 µA | 3 |
| Power dissipation at TA = 25°C (PW package) | PD | | | 400 | mW | TA = 25°C | 3 |
| Junction operating temperature | TJ | -55 | | 150 | °C | | 3 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 3 |
| Lead temperature (soldering) | | | | 300 | °C | Soldering 10 seconds | 3 |
| Operating free-air temperature (UCC3808x) | TA | 0 | | 70 | °C | UCC38084PW (UCC3808x family) | 3 |
| Start-up current | | | 120 | 200 | µA | VDD < UVLO start threshold voltage | 3 |
| Supply current | | | 1.5 | 2.5 | mA | CTRL = 0 V, CS = 0 V, See Note 1 | 3 |
| Start threshold voltage UCC38084/6 | | 4.1 | 4.3 | 4.5 | V | See Note 1 | 3 |
| Minimum operating voltage after start UCC38084/6 | | 3.9 | 4.1 | 4.3 | V | | 3 |
| Hysteresis voltage UCC38084/6 | | 0.1 | 0.2 | 0.3 | V | | 3 |
| Oscillator frequency | 2 x f(OUTA) | 180 | 200 | 220 | kHz | | 3 |
| Oscillator voltage amplitude | | 1.4 | 1.5 | 1.6 | V | See Note 2 | 3 |
| Oscillator fall time (dead time) | | | 110 | 220 | ns | | 3 |
| RT pin voltage | RT | 1.2 | 1.5 | 1.6 | V | | 3 |
| Current sense gain | | 1.9 | 2.2 | 2.5 | V/V | See Note 3 | 4 |
| Maximum input signal voltage | | 0.47 | 0.52 | 0.57 | V | CTRL = 5 V, See Note 4 | 4 |
| CS to output delay time | | | 100 | 200 | ns | CTRL = 3.5 V, 0 mV ≤ CS ≤ 600 mV | 4 |
| Source current | | | | -200 | nA | | 4 |
| Sink current | | 3 | 7 | 12 | mA | CS = 0.5 V, RT = 2.0 V, See Note 5 | 4 |
| Overcurrent threshold voltage | | 0.7 | 0.75 | 0.8 | V | | 4 |
| CTRL to CS offset voltage (25°C) | | 0.55 | 0.7 | 0.9 | V | CS = 0 V, 25°C | 4 |
| CTRL to CS offset voltage | | 0.37 | 0.7 | 1.1 | V | CS = 0 V | 4 |
| Maximum duty cycle | | 48 | 49 | 50 | % | Measured at OUTA or OUTB, See Note 7 | 4 |
| Minimum duty cycle | | 0 | | | % | CTRL = 0 V | 4 |
| Low-level output voltage (OUTA or OUTB) | | | 0.5 | 1 | V | IOUT = 100 mA | 4 |
| High-level output voltage (OUTA or OUTB) | VDD − VOUT | | 0.5 | 1 | V | IOUT = −50 mA, See Note 6 | 4 |
| Output rise time | | | 25 | 60 | ns | CLOAD = 1 nF | 4 |
| Output fall time | | | 25 | 60 | ns | CLOAD = 1 nF | 4 |
| OUTA/OUTB soft-start interval time UCC38083/4 | | 1.3 | 3.5 | 8.5 | ms | CTRL = 1.8 V, CS = 0 V, Duty cycle from 0 to full, See Note 8 | 4 |
| Peak slope compensation ramp current IRAMP | IRAMP | 125 | 150 | 175 | µA | ISET, peak = 30 µA, Full duty cycle | 4 |
| Thermal resistance junction-to-case (PW) | θjc | | 32 | | °C/W | Note 2 (modeled data) | 2 |
| Thermal resistance junction-to-ambient (PW) | θja | 232 | | 257 | °C/W | Modeled data (Note 2): lower value 3x3 inch board, higher value 1x1 inch ground plane | 2 |
## CAD (KiCad official)
- Symbol: `UCC38084PWR`
- Footprint: `Package_SO:TSSOP-8_3x3mm_P0.65mm`
- 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files: `ucc38084pwr-etched.step` / `ucc38084pwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ucc38084pwr.step` / `ucc38084pwr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/ucc38084.pdf) (28 pp, sha256 `19bab60962d5c6f5`, retrieved 2026-10-08, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ucc38084pwr-datasheet.pdf)