main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 29d ago
viewers ucc3807d-3: viewers · Ray 29d ago
package.json Publish 0.1.0 · Ray 29d ago
page.json Set visibility: public · Ray 29d ago
README.md Publish 0.1.0 · Ray 29d ago
ucc3807d-3-etched.glb ucc3807d-3: factory component page (tier=lcsc) · Ray 29d ago
ucc3807d-3-etched.step ucc3807d-3: factory component page (tier=lcsc) · Ray 29d ago
ucc3807d-3-hero.glb ucc3807d-3: hero GLB from the etched model (keeps the MPN mark) · Ray 29d ago
ucc3807d-3-hero.overlay.json Publish 0.1.0 · Ray 29d ago
ucc3807d-3.glb Publish 0.1.0 · Ray 29d ago
ucc3807d-3.kicad_mod Publish 0.1.0 · Ray 29d ago
ucc3807d-3.kicad_sym Publish 0.1.0 · Ray 29d ago
ucc3807d-3.lbr Publish 0.1.0 · Ray 29d ago
ucc3807d-3.step Publish 0.1.0 · Ray 29d ago

UCC3807D-3

Texas Instruments · DC-DC Converters · SOIC-8

UCC3807D-3 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TRIG input Oscillator timing input with an RC-type charge/discharge signal controlling the internal oscillator; signal minimum 1/3 VDD, maximum 2/3 VDD, with CT connected here.
2 COMP output Output of the error amplifier and input of the PWM comparator; it can source and sink current and is internally current limited, so forcing COMP to GND gives zero duty cycle.
3 FB input Inverting input to the error amplifier (2.0V reference); keep connections short and stray capacitance small for best stability.
4 CS input Current sense input to the PWM and overcurrent comparators (1.5V overcurrent threshold) with a 100ns leading edge blanking after the rising edge of OUT.
5 GND power_in Reference ground and power ground for all functions of the part.
6 OUT output Totem pole output of a high current power driver capable of driving a power MOSFET gate with peak currents exceeding 1A, actively held low when VDD is below the UVLO threshold.
7 VDD power_in Power input connection; bypass to GND with a ceramic capacitor close to the chip in parallel with an electrolytic, with a 13.5V typical zener shunt.
8 DISCH output Low impedance discharge path for the external RC timing network during normal operation, used to set oscillator frequency and maximum duty cycle.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Power Management (PMIC)
Pins 8

CAD (KiCad official)

  • Symbol: UCC3807D-3
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ucc3807d-3-etched.step / ucc3807d-3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc3807d-3.step / ucc3807d-3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (15 pp, sha256 18e438c9fefd4905, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF