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UCC35702D

Texas Instruments · AC-DC Controllers And Regulators · SOIC-14

UCC35702D from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 COUNT passive Fault-count integrating capacitor node to ground; a voltage over 4V initiates a latched soft stop cycle, and a resistor to ground sets the discharge time constant.
2 ILIM input Pulse-by-pulse current limit input that terminates the PWM pulse above 200mV, and an input above 600mV initiates a latched soft stop cycle; absolute maximum input rating is 6V.
3 VDD power_in Supply pin whose internal shunt regulator clamps VDD to about 14V typical at 10mA shunt current; supply current must be limited to less than 20mA when the clamp is active, and the absolute maximum supply voltage is 15V.
4 OUT output Gate drive output capable of 1A peak current with 10 ohm maximum output resistance; DC output current is limited to +/-180mA absolute maximum.
5 PGND power_in Power ground return for the output driver and its currents, which must connect to GND through a single path on the board.
6 VFF input Voltage feedforward input connected to the input line through a resistive divider, operational over 0.8V to 3.2V; voltages below 0.6V or above 4.0V initiate a soft stop cycle.
7 RT passive Timing resistor pin that mirrors VFF over 0.8V to 3.2V and sets the ramp capacitor charge current; the resistor to ground should be between 20k and 200k.
8 FB input PWM comparator input intended for an optocoupler drive, with 50k typical input impedance and 1.6V to 3.6V typical modulation range; absolute maximum input rating is 6V.
9 VSCLAMP input Volt-second clamp input compared against the CT ramp to terminate the PWM pulse and set the maximum on-time; absolute maximum input rating is 6V.
10 CT passive Oscillator and feedforward timing capacitor to ground, producing a sawtooth ramp from GND to VRT.
11 SYNC input Level-sensitive oscillator sync input with a 1.5V threshold where a high level forces the gate output low and resets the ramp, with an internal 3uA pull-down and absolute maximum input rating of 6V.
12 VREF power_out 5.0V trimmed reference with 2% variation over line, load and temperature, which must be bypassed with at least 0.1uF to ground.
13 GND power_in Analog ground return for all control circuits, which must be connected directly to PGND on the board.
14 SS passive Soft start capacitor pin charged to VREF by a nominal 18uA current source after power-up, and discharged at about 500uA during soft stop on High Line or Low Line faults.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Power Management (PMIC)
Pins 14

CAD (KiCad official)

  • Symbol: UCC35702D
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: ucc35702d-etched.step / ucc35702d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc35702d.step / ucc35702d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 458a65b2f0db2226, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF