component
UCC35702D
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+50@@ -0,0 +1,50 @@+# UCC35702D++**Texas Instruments** · AC-DC Controllers And Regulators · SOIC-14++UCC35702D from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | COUNT | passive | Fault-count integrating capacitor node to ground; a voltage over 4V initiates a latched soft stop cycle, and a resistor to ground sets the discharge time constant. |+| 2 | ILIM | input | Pulse-by-pulse current limit input that terminates the PWM pulse above 200mV, and an input above 600mV initiates a latched soft stop cycle; absolute maximum input rating is 6V. |+| 3 | VDD | power_in | Supply pin whose internal shunt regulator clamps VDD to about 14V typical at 10mA shunt current; supply current must be limited to less than 20mA when the clamp is active, and the absolute maximum supply voltage is 15V. |+| 4 | OUT | output | Gate drive output capable of 1A peak current with 10 ohm maximum output resistance; DC output current is limited to +/-180mA absolute maximum. |+| 5 | PGND | power_in | Power ground return for the output driver and its currents, which must connect to GND through a single path on the board. |+| 6 | VFF | input | Voltage feedforward input connected to the input line through a resistive divider, operational over 0.8V to 3.2V; voltages below 0.6V or above 4.0V initiate a soft stop cycle. |+| 7 | RT | passive | Timing resistor pin that mirrors VFF over 0.8V to 3.2V and sets the ramp capacitor charge current; the resistor to ground should be between 20k and 200k. |+| 8 | FB | input | PWM comparator input intended for an optocoupler drive, with 50k typical input impedance and 1.6V to 3.6V typical modulation range; absolute maximum input rating is 6V. |+| 9 | VSCLAMP | input | Volt-second clamp input compared against the CT ramp to terminate the PWM pulse and set the maximum on-time; absolute maximum input rating is 6V. |+| 10 | CT | passive | Oscillator and feedforward timing capacitor to ground, producing a sawtooth ramp from GND to VRT. |+| 11 | SYNC | input | Level-sensitive oscillator sync input with a 1.5V threshold where a high level forces the gate output low and resets the ramp, with an internal 3uA pull-down and absolute maximum input rating of 6V. |+| 12 | VREF | power_out | 5.0V trimmed reference with 2% variation over line, load and temperature, which must be bypassed with at least 0.1uF to ground. |+| 13 | GND | power_in | Analog ground return for all control circuits, which must be connected directly to PGND on the board. |+| 14 | SS | passive | Soft start capacitor pin charged to VREF by a nominal 18uA current source after power-up, and discharged at about 500uA during soft stop on High Line or Low Line faults. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-14 |+| Category | Power Management (PMIC) |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `UCC35702D`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)+- 3D model files: `ucc35702d-etched.step` / `ucc35702d-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ucc35702d.step` / `ucc35702d.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ucc35702) (23 pp, sha256 `458a65b2f0db2226`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ucc35702d-datasheet.pdf)
page.jsonadded+235@@ -0,0 +1,235 @@+{+ "slug": "ucc35702d",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments AC-DC Controllers And Regulators, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "ucc35702d",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ucc35702d.kicad_sym",+ "ucc35702d.kicad_mod",+ "ucc35702d.glb",+ "ucc35702d.step",+ "ucc35702d.lbr",+ "docs/hero.png",+ "docs/ucc35702d-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "ucc35702d-hero.glb",+ "ucc35702d-hero.overlay.json"+ ],+ "component": {+ "mpn": "UCC35702D",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-14",+ "pin_count": 14,+ "category": "Power Management (PMIC)",+ "subcategory": "AC-DC Controllers And Regulators",+ "datasheet": "https://www.ti.com/cn/lit/gpn/ucc35702",+ "parts": {+ "symbol": "ucc35702d.kicad_sym",+ "footprint": "ucc35702d.kicad_mod",+ "model_3d": "ucc35702d-hero.glb",+ "model_3d_plain": "ucc35702d.glb",+ "model_3d_step": "ucc35702d-etched.step",+ "model_3d_step_plain": "ucc35702d.step",+ "lbr": "ucc35702d.lbr"+ },+ "distributor_links": {+ "lcsc": "C2864327",+ "digikey": "2156-UCC35702D-TI-ND",+ "mouser": "595-UCC35702D"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T16:33:17Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "2156-UCC35702D-TI-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-UCC35702D",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "COUNT",+ "type": "passive",+ "description": "Fault-count integrating capacitor node to ground; a voltage over 4V initiates a latched soft stop cycle, and a resistor to ground sets the discharge time constant."+ },+ {+ "number": "2",+ "name": "ILIM",+ "type": "input",+ "description": "Pulse-by-pulse current limit input that terminates the PWM pulse above 200mV, and an input above 600mV initiates a latched soft stop cycle; absolute maximum input rating is 6V."+ },+ {+ "number": "3",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply pin whose internal shunt regulator clamps VDD to about 14V typical at 10mA shunt current; supply current must be limited to less than 20mA when the clamp is active, and the absolute maximum supply voltage is 15V."+ },+ {+ "number": "4",+ "name": "OUT",+ "type": "output",+ "description": "Gate drive output capable of 1A peak current with 10 ohm maximum output resistance; DC output current is limited to +/-180mA absolute maximum."+ },+ {+ "number": "5",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground return for the output driver and its currents, which must connect to GND through a single path on the board."+ },+ {+ "number": "6",+ "name": "VFF",+ "type": "input",+ "description": "Voltage feedforward input connected to the input line through a resistive divider, operational over 0.8V to 3.2V; voltages below 0.6V or above 4.0V initiate a soft stop cycle."+ },+ {+ "number": "7",+ "name": "RT",+ "type": "passive",+ "description": "Timing resistor pin that mirrors VFF over 0.8V to 3.2V and sets the ramp capacitor charge current; the resistor to ground should be between 20k and 200k."+ },+ {+ "number": "8",+ "name": "FB",+ "type": "input",+ "description": "PWM comparator input intended for an optocoupler drive, with 50k typical input impedance and 1.6V to 3.6V typical modulation range; absolute maximum input rating is 6V."+ },+ {+ "number": "9",+ "name": "VSCLAMP",+ "type": "input",+ "description": "Volt-second clamp input compared against the CT ramp to terminate the PWM pulse and set the maximum on-time; absolute maximum input rating is 6V."+ },+ {+ "number": "10",+ "name": "CT",+ "type": "passive",+ "description": "Oscillator and feedforward timing capacitor to ground, producing a sawtooth ramp from GND to VRT."+ },+ {+ "number": "11",+ "name": "SYNC",+ "type": "input",+ "description": "Level-sensitive oscillator sync input with a 1.5V threshold where a high level forces the gate output low and resets the ramp, with an internal 3uA pull-down and absolute maximum input rating of 6V."+ },+ {+ "number": "12",+ "name": "VREF",+ "type": "power_out",+ "description": "5.0V trimmed reference with 2% variation over line, load and temperature, which must be bypassed with at least 0.1uF to ground."+ },+ {+ "number": "13",+ "name": "GND",+ "type": "power_in",+ "description": "Analog ground return for all control circuits, which must be connected directly to PGND on the board."+ },+ {+ "number": "14",+ "name": "SS",+ "type": "passive",+ "description": "Soft start capacitor pin charged to VREF by a nominal 18uA current source after power-up, and discharged at about 500uA during soft stop on High Line or Low Line faults."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The connection diagram text in the datasheet extraction is scrambled. Pin numbers were assigned by c; Pin types for passive-type nodes (COUNT, RT, CT, SS) are assigned as passive because they are timing"+ ],+ "pages_sent": 23,+ "cost_usd": 0.1077,+ "at": "2026-10-08T16:32:58"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ucc35702",+ "pages": 23,+ "sha256": "458a65b2f0db2226",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "ucc35702d.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 8.7,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "ucc35702d-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 8.7,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "15443505076a6c5dfa7cab462f28ce006ab7c3924d0fce7caa9c2bf4bedf0698",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}