component
UCC28C57HQDRQ1
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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UCC28C57HQDRQ1
Texas Instruments · AC-DC Controllers And Regulators · SOIC-8
UCC28C57HQDRQ1 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier output for compensation that can source and sink current, and it is internally current limited so forcing COMP to GND commands zero duty cycle. |
| 2 | FB | input | Inverting input to the error amplifier, whose noninverting reference is internally trimmed to 2.5 V ±1%. |
| 3 | CS | input | Primary-side current sense input to the PWM comparator that terminates OUT conduction, with a typical current sense amplifier gain of 3 V/V. |
| 4 | RT/CT | bidirectional | Oscillator timing pin where a resistor from VREF and a capacitor to GND set the switching frequency, with recommended timing resistors of 1 kΩ to 100 kΩ and timing capacitors of 220 pF to 4.7 nF. |
| 5 | GND | power_in | Ground return pin for the output driver stage and the logic level controller section. |
| 6 | OUT | output | Totem-pole gate drive output that sources and sinks up to 1 A peak and is held low when VDD is below the turn-on threshold, and for this UCC28C57H variant its frequency is one-half the oscillator, limiting duty cycle to below 50%. |
| 7 | VDD | power_in | Analog controller bias supply input with a 30 V absolute maximum rating that requires a typical 0.1 µF bypass capacitor connected directly to GND. |
| 8 | VREF | power_out | 5-V reference output that requires a minimum 0.1 µF ceramic bypass capacitor to GND placed as close to the pin as possible. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage VDD | VDD | 30 | V | 5 | |||
| Input current IVDD | IVDD | 30 | mA | 5 | |||
| Output drive current (peak) | -1 | 1 | A | 5 | |||
| Analog input voltage COMP, CS, FB, RT/CT | -0.3 | 6.3 | V | 5 | |||
| Output driver voltage OUT | -0.3 | 30 | V | 5 | |||
| Reference voltage VREF | VREF | 7 | V | 5 | |||
| Error amplifier output sink current COMP | 10 | mA | 5 | ||||
| Operating junction temperature | TJ | -40 | 150 | °C | 5 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| Input voltage VDD | VVDD | 28 | V | 6 | |||
| Output driver voltage | VOUT | 28 | V | 6 | |||
| Average output driver current | IOUT | 200 | mA | 6 | |||
| Reference output current | IOUT(VREF) | -20 | mA | 6 | |||
| Operating junction temperature | TJ | -40 | 150 | °C | UCC28C5x-Q1 | 6 | |
| Operating ambient temperature | TA | -40 | 125 | °C | UCC28C5x-Q1 | 6 | |
| Junction-to-ambient thermal resistance | RθJA | 128.9 | °C/W | D (SOIC) 8 pins | 6 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 71.7 | °C/W | D (SOIC) 8 pins | 6 | ||
| Junction-to-board thermal resistance | RθJB | 72.3 | °C/W | D (SOIC) 8 pins | 6 | ||
| VREF voltage, initial accuracy | VVREF | 4.95 | 5 | 5.05 | V | IOUT = 1 mA | 7 |
| Line regulation | 0.2 | 20 | mV | VVDD = 12 V to 25 V | 7 | ||
| Load regulation | 3 | 25 | mV | 1 mA to 20 mA | 7 | ||
| Total output variation | 4.82 | 5.18 | V | See (2) | 7 | ||
| Output short circuit (source current) | IVREF | 30 | 45 | 55 | mA | 7 | |
| Temperature stability | 0.2 | 0.4 | mV/°C | See (2) | 7 | ||
| Initial accuracy fOSC | fOSC | 50.5 | 53 | 55 | kHz | TJ = 25°C, see (3) | 7 |
| Initial accuracy fOSC full range | fOSC | 50.5 | 57 | kHz | TJ = Full Range, see (3) | 7 | |
| Voltage stability | 0.2 | 1 | % | 12 V ≤ VVDD ≤ 25 V | 7 | ||
| Temperature stability | 1 | 2.5 | % | TJ(MIN) to TJ(MAX), see (2) | 7 | ||
| Discharge current | 7.7 | 8.4 | 9 | mA | TJ = 25°C, VRT/CT = 2 V, see (4) | 7 | |
| Discharge current full range | 7.2 | 8.4 | 9.5 | mA | TJ = Full Range, VRT/CT = 2 V, see (4) | 7 | |
| Feedback input voltage, initial accuracy | VFB | 2.475 | 2.5 | 2.525 | V | TJ = 25°C, VCOMP = 2.5 V | 7 |
| Feedback input voltage, total variation | VFB | 2.45 | 2.5 | 2.55 | V | TJ = Full Range, VCOMP = 2.5 V | 7 |
| Input bias current | IFB | 0.1 | 2 | µA | VFB = 5 V, (sourcing current) | 7 | |
| Open-loop voltage gain | AVOL | 65 | dB | 2 V ≤ VOUT ≤ 4 V | 7 | ||
| Unity gain bandwidth | 1 | 1.5 | MHz | See (2) | 7 | ||
| Output sink current | 2 | 14 | mA | VFB = 2.7 V, VCOMP = 1.1 V | 7 | ||
| Output source current | 0.5 | 1 | mA | VFB = 2.3 V, VCOMP = 5 V, (sourcing current) | 7 | ||
| Gain TJ = 25°C | ACS | 2.85 | 3 | 3.15 | V/V | TJ = 25°C, See (5) | 7 |
| Gain full range | ACS | 2.75 | 3 | 3.15 | V/V | TJ = Full Range, See (5) | 7 |
| Maximum input signal | VCS | 0.9 | 1 | 1.1 | V | VFB < 2.4 V | 7 |
| Input bias current (source current) | ICS | 0.1 | 2 | µA | 7 | ||
| CS to output delay | tD | 35 | 70 | ns | 7 | ||
| RDS(on) pulldown | VOUT(low) | 5.5 | 15 | Ω | ISINK = 200 mA | 7 | |
| RDS(on) pullup | VOUT(high) | 10 | 25 | Ω | ISOURCE = 200 mA | 7 | |
| Rise time | tRISE | 25 | 50 | ns | TJ = 25°C, COUT = 1 nF | 7 | |
| Fall time | tFALL | 20 | 40 | ns | TJ = 25°C, COUT = 1 nF | 7 | |
| Start threshold UCC28C56H-Q1, UCC28C57H-Q1 | VDDON | 17.6 | 18.8 | 20 | V | Start threshold | 8 |
| Minimum operating voltage UCC28C56H-Q1, UCC28C57H-Q1 | VDDOFF | 15 | 15.5 | 16 | V | Minimum operating voltage | 8 |
| Hysteresis UCC28C56H-Q1, UCC28C57H-Q1 | VDDHyst | 2.6 | 3.3 | V | VDDON - VDDOFF | 8 | |
| Start-up current | ISTART-UP | 50 | 75 | µA | VVDD = VDDON, 0.5 V | 8 | |
| Operating supply current | IVDD | 1.3 | 2 | mA | VFB = VCS = 0 V | 8 | |
| Maximum duty cycle UCC28C57H-Q1, UCC28C57L-Q1, UCC28C59-Q1 | DMAX | 47 | 48 | % | VFB < 2.4 V | 8 |
CAD (KiCad official)
- Symbol:
UCC28C57HQDRQ1 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ucc28c57hqdrq1-etched.step/ucc28c57hqdrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucc28c57hqdrq1.step/ucc28c57hqdrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (54 pp, sha256
bc676a96b11f3510, retrieved 2026-11-06, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# UCC28C57HQDRQ1
**Texas Instruments** · AC-DC Controllers And Regulators · SOIC-8
UCC28C57HQDRQ1 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier output for compensation that can source and sink current, and it is internally current limited so forcing COMP to GND commands zero duty cycle. |
| 2 | FB | input | Inverting input to the error amplifier, whose noninverting reference is internally trimmed to 2.5 V ±1%. |
| 3 | CS | input | Primary-side current sense input to the PWM comparator that terminates OUT conduction, with a typical current sense amplifier gain of 3 V/V. |
| 4 | RT/CT | bidirectional | Oscillator timing pin where a resistor from VREF and a capacitor to GND set the switching frequency, with recommended timing resistors of 1 kΩ to 100 kΩ and timing capacitors of 220 pF to 4.7 nF. |
| 5 | GND | power_in | Ground return pin for the output driver stage and the logic level controller section. |
| 6 | OUT | output | Totem-pole gate drive output that sources and sinks up to 1 A peak and is held low when VDD is below the turn-on threshold, and for this UCC28C57H variant its frequency is one-half the oscillator, limiting duty cycle to below 50%. |
| 7 | VDD | power_in | Analog controller bias supply input with a 30 V absolute maximum rating that requires a typical 0.1 µF bypass capacitor connected directly to GND. |
| 8 | VREF | power_out | 5-V reference output that requires a minimum 0.1 µF ceramic bypass capacitor to GND placed as close to the pin as possible. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage VDD | VDD | | | 30 | V | | 5 |
| Input current IVDD | IVDD | | | 30 | mA | | 5 |
| Output drive current (peak) | | -1 | | 1 | A | | 5 |
| Analog input voltage COMP, CS, FB, RT/CT | | -0.3 | | 6.3 | V | | 5 |
| Output driver voltage OUT | | -0.3 | | 30 | V | | 5 |
| Reference voltage VREF | VREF | | | 7 | V | | 5 |
| Error amplifier output sink current COMP | | | | 10 | mA | | 5 |
| Operating junction temperature | TJ | -40 | | 150 | °C | | 5 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 5 |
| Input voltage VDD | VVDD | | | 28 | V | | 6 |
| Output driver voltage | VOUT | | | 28 | V | | 6 |
| Average output driver current | IOUT | | | 200 | mA | | 6 |
| Reference output current | IOUT(VREF) | -20 | | | mA | | 6 |
| Operating junction temperature | TJ | -40 | | 150 | °C | UCC28C5x-Q1 | 6 |
| Operating ambient temperature | TA | -40 | | 125 | °C | UCC28C5x-Q1 | 6 |
| Junction-to-ambient thermal resistance | RθJA | | 128.9 | | °C/W | D (SOIC) 8 pins | 6 |
| Junction-to-case (top) thermal resistance | RθJC(top) | | 71.7 | | °C/W | D (SOIC) 8 pins | 6 |
| Junction-to-board thermal resistance | RθJB | | 72.3 | | °C/W | D (SOIC) 8 pins | 6 |
| VREF voltage, initial accuracy | VVREF | 4.95 | 5 | 5.05 | V | IOUT = 1 mA | 7 |
| Line regulation | | | 0.2 | 20 | mV | VVDD = 12 V to 25 V | 7 |
| Load regulation | | | 3 | 25 | mV | 1 mA to 20 mA | 7 |
| Total output variation | | 4.82 | | 5.18 | V | See (2) | 7 |
| Output short circuit (source current) | IVREF | 30 | 45 | 55 | mA | | 7 |
| Temperature stability | | | 0.2 | 0.4 | mV/°C | See (2) | 7 |
| Initial accuracy fOSC | fOSC | 50.5 | 53 | 55 | kHz | TJ = 25°C, see (3) | 7 |
| Initial accuracy fOSC full range | fOSC | 50.5 | | 57 | kHz | TJ = Full Range, see (3) | 7 |
| Voltage stability | | | 0.2 | 1 | % | 12 V ≤ VVDD ≤ 25 V | 7 |
| Temperature stability | | | 1 | 2.5 | % | TJ(MIN) to TJ(MAX), see (2) | 7 |
| Discharge current | | 7.7 | 8.4 | 9 | mA | TJ = 25°C, VRT/CT = 2 V, see (4) | 7 |
| Discharge current full range | | 7.2 | 8.4 | 9.5 | mA | TJ = Full Range, VRT/CT = 2 V, see (4) | 7 |
| Feedback input voltage, initial accuracy | VFB | 2.475 | 2.5 | 2.525 | V | TJ = 25°C, VCOMP = 2.5 V | 7 |
| Feedback input voltage, total variation | VFB | 2.45 | 2.5 | 2.55 | V | TJ = Full Range, VCOMP = 2.5 V | 7 |
| Input bias current | IFB | | 0.1 | 2 | µA | VFB = 5 V, (sourcing current) | 7 |
| Open-loop voltage gain | AVOL | 65 | | | dB | 2 V ≤ VOUT ≤ 4 V | 7 |
| Unity gain bandwidth | | | 1 | 1.5 | MHz | See (2) | 7 |
| Output sink current | | 2 | | 14 | mA | VFB = 2.7 V, VCOMP = 1.1 V | 7 |
| Output source current | | 0.5 | | 1 | mA | VFB = 2.3 V, VCOMP = 5 V, (sourcing current) | 7 |
| Gain TJ = 25°C | ACS | 2.85 | 3 | 3.15 | V/V | TJ = 25°C, See (5) | 7 |
| Gain full range | ACS | 2.75 | 3 | 3.15 | V/V | TJ = Full Range, See (5) | 7 |
| Maximum input signal | VCS | 0.9 | 1 | 1.1 | V | VFB < 2.4 V | 7 |
| Input bias current (source current) | ICS | | 0.1 | 2 | µA | | 7 |
| CS to output delay | tD | | 35 | 70 | ns | | 7 |
| RDS(on) pulldown | VOUT(low) | | 5.5 | 15 | Ω | ISINK = 200 mA | 7 |
| RDS(on) pullup | VOUT(high) | | 10 | 25 | Ω | ISOURCE = 200 mA | 7 |
| Rise time | tRISE | | 25 | 50 | ns | TJ = 25°C, COUT = 1 nF | 7 |
| Fall time | tFALL | | 20 | 40 | ns | TJ = 25°C, COUT = 1 nF | 7 |
| Start threshold UCC28C56H-Q1, UCC28C57H-Q1 | VDDON | 17.6 | 18.8 | 20 | V | Start threshold | 8 |
| Minimum operating voltage UCC28C56H-Q1, UCC28C57H-Q1 | VDDOFF | 15 | 15.5 | 16 | V | Minimum operating voltage | 8 |
| Hysteresis UCC28C56H-Q1, UCC28C57H-Q1 | VDDHyst | 2.6 | 3.3 | | V | VDDON - VDDOFF | 8 |
| Start-up current | ISTART-UP | | 50 | 75 | µA | VVDD = VDDON, 0.5 V | 8 |
| Operating supply current | IVDD | | 1.3 | 2 | mA | VFB = VCS = 0 V | 8 |
| Maximum duty cycle UCC28C57H-Q1, UCC28C57L-Q1, UCC28C59-Q1 | DMAX | 47 | | 48 | % | VFB < 2.4 V | 8 |
## CAD (KiCad official)
- Symbol: `UCC28C57HQDRQ1`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ucc28c57hqdrq1-etched.step` / `ucc28c57hqdrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ucc28c57hqdrq1.step` / `ucc28c57hqdrq1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/ucc28c57h-q1.pdf) (54 pp, sha256 `bc676a96b11f3510`, retrieved 2026-11-06, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ucc28c57hqdrq1-datasheet.pdf)