component
UCC28C55DR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownUCC28C55DR
Texas Instruments · DC-DC Converters · SOIC-8
UCC28C55DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier output for compensation and secondary error signal injection; internally current-limited to allow zero duty cycle forcing by external pull-to-GND. |
| 2 | FB | input | Inverting input to error amplifier with internally trimmed 2.5V ±1% reference for closed-loop output voltage feedback control and stability. |
| 3 | CS | input | Primary-side current sense input to PWM comparator noninverting input for cycle-by-cycle current limiting with 1V typical threshold and duty cycle termination. |
| 4 | RT/CT | bidirectional | Oscillator timing node; connect timing resistor to VREF and timing capacitor to GND to program switching frequency and set maximum duty cycle dead time. |
| 5 | GND | power_in | Ground return pin for output driver stage and logic level controller section; connect as close to signal return path as possible to minimize noise coupling. |
| 6 | OUT | output | Output driver stage with ±1A peak current capability for direct MOSFET gate drive; held actively low during UVLO and operates at one-half oscillator frequency in UCCx8C55. |
| 7 | VDD | power_in | Analog controller bias input with 30V absolute maximum rating and total current equal to sum of quiescent current and average OUT current; requires 0.1µF bypass capacitor to GND. |
| 8 | VREF | power_in | 5V precision reference voltage with ±1% initial accuracy (±2% over full temperature) for oscillator timing charging current and internal bias thresholds; requires 0.1µF ceramic bypass capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
UCC28C55DR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ucc28c55dr-etched.step/ucc28c55dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucc28c55dr.step/ucc28c55dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (58 pp, sha256
d9b2cab289f0aa82, retrieved 2026-09-26, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).