UCC28C53QDRQ1

Texas Instruments · DC-DC Converters · SOIC-8

UCC28C53QDRQ1 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	COMP	output	Error amplifier output for compensation that can both source and sink current, is internally current-limited, and can be forced to GND to command zero duty cycle.
2	FB	input	Inverting input of the error amplifier, with the non-inverting input internally trimmed to 2.5 V ±1%.
3	CS	input	Primary-side current sense input to the PWM comparator that terminates OUT conduction, with a typical current sense amplifier gain of 3 V/V.
4	RT/CT	bidirectional	Oscillator timing pin where a resistor from VREF and a capacitor to GND set the fixed switching frequency, with TI recommending 1 kΩ to 100 kΩ resistors and 220 pF to 4.7 nF capacitors for operation up to 1 MHz.
5	GND	power_in	Ground return for the output driver stage and the logic-level controller section, which TI recommends keeping separate from the signal return path.
6	OUT	output	Totem-pole gate drive output that sources and sinks up to 1 A peak, is held low when VDD is below the turn-on threshold, and for UCC28C53 switches at the oscillator frequency and can operate near 100% duty cycle.
7	VDD	power_in	Analog controller bias supply input whose total current is the quiescent VDD current plus the average OUT current, and which requires a minimum 0.1 µF bypass capacitor connected directly to GND.
8	VREF	power_out	5-V reference output that requires a minimum 0.1 µF ceramic bypass placed as close to the pin as possible, and no external voltage higher than VREF may be superimposed on it.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-8
Category	Power Management (PMIC)
Pins	8

CAD (KiCad official)

Symbol: UCC28C53QDRQ1
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: ucc28c53qdrq1-etched.step / ucc28c53qdrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc28c53qdrq1.step / ucc28c53qdrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (54 pp, sha256 17e157e3c78ffd7e, retrieved 2026-10-10, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# UCC28C53QDRQ1

**Texas Instruments** · DC-DC Converters · SOIC-8

UCC28C53QDRQ1 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier output for compensation that can both source and sink current, is internally current-limited, and can be forced to GND to command zero duty cycle. |
| 2 | FB | input | Inverting input of the error amplifier, with the non-inverting input internally trimmed to 2.5 V ±1%. |
| 3 | CS | input | Primary-side current sense input to the PWM comparator that terminates OUT conduction, with a typical current sense amplifier gain of 3 V/V. |
| 4 | RT/CT | bidirectional | Oscillator timing pin where a resistor from VREF and a capacitor to GND set the fixed switching frequency, with TI recommending 1 kΩ to 100 kΩ resistors and 220 pF to 4.7 nF capacitors for operation up to 1 MHz. |
| 5 | GND | power_in | Ground return for the output driver stage and the logic-level controller section, which TI recommends keeping separate from the signal return path. |
| 6 | OUT | output | Totem-pole gate drive output that sources and sinks up to 1 A peak, is held low when VDD is below the turn-on threshold, and for UCC28C53 switches at the oscillator frequency and can operate near 100% duty cycle. |
| 7 | VDD | power_in | Analog controller bias supply input whose total current is the quiescent VDD current plus the average OUT current, and which requires a minimum 0.1 µF bypass capacitor connected directly to GND. |
| 8 | VREF | power_out | 5-V reference output that requires a minimum 0.1 µF ceramic bypass placed as close to the pin as possible, and no external voltage higher than VREF may be superimposed on it. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |

## CAD (KiCad official)

- Symbol: `UCC28C53QDRQ1`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ucc28c53qdrq1-etched.step` / `ucc28c53qdrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ucc28c53qdrq1.step` / `ucc28c53qdrq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590923826085502976) (54 pp, sha256 `17e157e3c78ffd7e`, retrieved 2026-10-10, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ucc28c53qdrq1-datasheet.pdf)