component
UCC28C51QDRQ1
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 18h ago |
| viewers | 18h ago |
| package.json | 18h ago |
| page.json | 18h ago |
| README.md | 18h ago |
| ucc28c51qdrq1-etched.glb | 18h ago |
| ucc28c51qdrq1-etched.step | 18h ago |
| ucc28c51qdrq1-hero.glb | 18h ago |
| ucc28c51qdrq1-hero.overlay.json | 18h ago |
| ucc28c51qdrq1.glb | 18h ago |
| ucc28c51qdrq1.kicad_mod | 18h ago |
| ucc28c51qdrq1.kicad_sym | 18h ago |
| ucc28c51qdrq1.lbr | 18h ago |
| ucc28c51qdrq1.step | 18h ago |
UCC28C51QDRQ1
Texas Instruments · AC-DC Controllers And Regulators · SOIC-8
UCC28C51QDRQ1 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier output providing compensation signal and control port for secondary isolation with internal current limiting to enable zero duty cycle command. |
| 2 | FB | input | Inverting input to error amplifier with 2.5 V ±1% internally-trimmed noninverting reference for voltage-feedback loop control. |
| 3 | CS | input | Primary-side current sense input to PWM comparator comparing sensed current against error amplifier signal to control switch conduction termination. |
| 4 | RT/CT | bidirectional | Oscillator timing pin for fixed-frequency operation via external resistor to VREF and capacitor to GND; switching frequency equals half fOSC for UCC28C51-Q1. |
| 5 | GND | power_in | Ground return pin for the output driver stage and the logic level controller section. |
| 6 | OUT | output | MOSFET gate driver output sourcing/sinking 1 A peak current at half fOSC frequency with <50% maximum duty cycle and active-low behavior below UVLO threshold for UCC28C51-Q1. |
| 7 | VDD | power_in | Analog controller bias input (0-30 V max) providing power to device; requires 0.1 µF bypass capacitor to GND with minimal trace and additional bulk capacitance. |
| 8 | VREF | power_out | 5-V regulated reference output providing charging current to oscillator timing capacitor through external resistor; requires minimum 0.1 µF ceramic bypass capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
UCC28C51QDRQ1 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ucc28c51qdrq1-etched.step/ucc28c51qdrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucc28c51qdrq1.step/ucc28c51qdrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (54 pp, sha256
17e157e3c78ffd7e, retrieved 2026-10-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).