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UCC28C51DR

Public Made by Adom

by adom

Texas Instruments DC-DC Converters, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)ucc28c51drfactory-2.0.0extractor-text
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Contents

README

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UCC28C51DR

Texas Instruments · DC-DC Converters · SOIC-8

UCC28C51DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 COMP output Error amplifier output for compensation, internally current limited so zero duty cycle can be commanded by forcing COMP to GND.
2 FB input Inverting input of the error amplifier used for the voltage-feedback loop, with the noninverting input internally trimmed to 2.5 V ±1%.
3 CS input Primary-side current sense input to the PWM comparator, connected to the current sensing resistor, abs max input -0.3 to 6.3 V.
4 RT/CT passive Oscillator set point: timing resistor to VREF and timing capacitor to GND set the switching frequency, abs max input -0.3 to 6.3 V.
5 GND power_in Ground return for the output driver stage and the logic level controller section.
6 OUT output Totem-pole gate driver output sourcing and sinking up to 1 A peak, at half the oscillator frequency (<50% duty cycle) in UCC28C51, held low when VDD is below turn-on threshold.
7 VDD power_in Controller bias supply input with 30 V absolute maximum, requiring a 0.1 µF bypass capacitor directly to GND.
8 VREF power_out 5-V reference output (±1%) charging the timing capacitor through the timing resistor, requiring at least 0.1 µF ceramic bypass to GND, abs max 7 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VREF voltage, initial accuracy VVREF 4.95 5 5.05 V TJ = 25°C, IOUT = 1 mA 7
VREF total output variation 4.85 5.15 V Specified by design 7
VREF line regulation 0.2 20 mV 12 V ≤ VVDD ≤ 25 V 7
VREF load regulation 3 25 mV 1 mA to 20 mA 7
VREF output short circuit (source current) IVREF 30 45 55 mA 7
Oscillator initial accuracy fOSC 50.5 53 55 kHz TJ = 25°C 7
Oscillator discharge current 7.7 8.4 9 mA TJ = 25°C, VRT/CT = 2 V 7
Oscillator discharge current 7.2 8.4 9.5 mA VRT/CT = 2 V 7
Oscillator voltage stability 0.2 1 % 12 V ≤ VVDD ≤ 25 V 7
Oscillator temperature stability 1 2.5 % TJ(MIN) to TJ(MAX) 7
Feedback input voltage, initial accuracy VFB 2.475 2.5 2.525 V VCOMP = 2.5 V, TJ = 25°C 7
Feedback input voltage, total variation VFB 2.45 2.5 2.55 V VCOMP = 2.5 V 7
FB input bias current IFB 0.1 2 µA VFB = 5 V 7
Open-loop voltage gain AVOL 65 90 dB 2 V ≤ VOUT ≤ 4 V 7
Error amplifier output sink current 2 14 mA VFB = 2.7 V, VCOMP = 1.1 V 7
Error amplifier output source current 0.5 1 mA VFB = 2.3 V, VCOMP = 5 V 7
Low-level COMP voltage VOL 0.1 1.1 V VFB = 2.7 V, RCOMP = 15 kΩ COMP to VREF 7
Current sense gain ACS 2.85 3 3.15 V/V 7
Current sense maximum input signal VCS 0.9 1 1.1 V VFB < 2.4 V 7
CS input bias current ICS 0.1 2 µA 7
CS to output delay tD 35 70 ns 7
OUT RDS(on) pulldown VOUT(low) 5.5 15 Ω ISINK = 200 mA 7
OUT RDS(on) pullup VOUT(high) 10 25 Ω ISOURCE = 200 mA 7
Rise time tRISE 25 50 ns TJ = 25°C, COUT = 1 nF 7
Fall time tFALL 20 40 ns TJ = 25°C, COUT = 1 nF 7
Start threshold VDDON 6.5 7 7.5 V UCCx8C51 8
Minimum operating voltage VDDOFF 6.1 6.6 7.1 V UCCx8C51 8
UVLO hysteresis VDDHyst 0.4 0.5 V VDDON - VDDOFF, UCCx8C51 8
Maximum duty cycle DMAX 47 48 % UCCx8C51, VFB < 2.4 V 8
Start-up current ISTART-UP 50 75 µA VVDD = VDDON, 0.5 V 8
Operating supply current IVDD 1.3 2 mA VFB = VCS = 0 V 8
Input voltage VDD VDD 30 V 5
Input current IVDD IVDD 30 mA 5
Output drive current (peak) -1 1 A 5
Output energy (capacitive load) EOUT 5 µJ 5
Analog input voltage -0.3 6.3 V COMP, CS, FB, RT/CT 5
Output driver voltage -0.3 30 V OUT 5
Reference voltage 7 V VREF 5
Error amplifier output sink current 10 mA COMP 5
Lead temperature TLEAD 300 °C soldering, 10 s 5
Operating junction temperature TJ -40 150 °C 5
Storage temperature Tstg -65 150 °C 5
Input voltage VVDD 28 V 6
Output driver voltage VOUT 28 V 6
Average output driver current IOUT 200 mA 6
Reference output current IOUT(VREF) -20 mA 6
Operating junction temperature TJ -40 125 °C UCC28C5x 6
Junction-to-ambient thermal resistance RθJA 128.9 °C/W D (SOIC) 8 pins 6
Junction-to-case (top) thermal resistance RθJC(top) 71.7 °C/W D (SOIC) 6
Junction-to-board thermal resistance RθJB 72.3 °C/W D (SOIC) 6
Junction-to-top characterization parameter ψJT 23.4 °C/W D (SOIC) 6
Junction-to-board characterization parameter ψJB 71.5 °C/W D (SOIC) 6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin The inductor rising slope (Sn) at the CS pin is calculated with Equation 34. Sn = 34

CAD (KiCad official)

  • Symbol: UCC28C51DR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ucc28c51dr-etched.step / ucc28c51dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc28c51dr.step / ucc28c51dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (58 pp, sha256 d9b2cab289f0aa82, retrieved 2026-10-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF