UCC28C50DR

Texas Instruments · AC-DC Controllers And Regulators · SOIC-8

UCC28C50DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	COMP	output	Provides the output of the error amplifier for compensation and can be externally forced to GND to command zero duty cycle, with the error amplifier internally current limited.
2	FB	input	Inverting input to the error amplifier used to close the voltage-feedback loop, with the noninverting input internally trimmed to 2.5 V ± 1%.
3	CS	input	Primary-side current sense input to the PWM comparator that terminates OUT conduction, with a typical gain of 3 V/V and an RC filter recommended if leading-edge noise causes false triggering.
4	RT/CT	bidirectional	Oscillator set point where timing resistor RRT connects to VREF and timing capacitor CCT connects to GND to set the switching frequency, with the capacitor lead kept short to the device GND.
5	GND	power_in	Ground return for the output driver stage and the logic-level controller section, which should be separated from the signal return path where practical.
6	OUT	output	Totem-pole gate drive output intended to drive a MOSFET directly, sourcing and sinking up to 1 A peak and held low when VDD is below the turn-on threshold.
7	VDD	power_in	Analog controller bias supply input, with absolute maximum 30 V, requiring a 0.1 µF ceramic bypass capacitor connected directly to GND and an absolute maximum of 30 V that must not be exceeded.
8	VREF	power_in	5-V reference output (±1%) that must be bypassed to GND with at least 0.1 µF ceramic placed close to the pin, and must not have any external voltage above the specified VREF superimposed on it.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-8
Category	Power Management (PMIC)
Pins	8

CAD (KiCad official)

Symbol: UCC28C50DR
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: ucc28c50dr-etched.step / ucc28c50dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc28c50dr.step / ucc28c50dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (58 pp, sha256 d9b2cab289f0aa82, retrieved 2026-10-08, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# UCC28C50DR

**Texas Instruments** · AC-DC Controllers And Regulators · SOIC-8

UCC28C50DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Provides the output of the error amplifier for compensation and can be externally forced to GND to command zero duty cycle, with the error amplifier internally current limited. |
| 2 | FB | input | Inverting input to the error amplifier used to close the voltage-feedback loop, with the noninverting input internally trimmed to 2.5 V ± 1%. |
| 3 | CS | input | Primary-side current sense input to the PWM comparator that terminates OUT conduction, with a typical gain of 3 V/V and an RC filter recommended if leading-edge noise causes false triggering. |
| 4 | RT/CT | bidirectional | Oscillator set point where timing resistor RRT connects to VREF and timing capacitor CCT connects to GND to set the switching frequency, with the capacitor lead kept short to the device GND. |
| 5 | GND | power_in | Ground return for the output driver stage and the logic-level controller section, which should be separated from the signal return path where practical. |
| 6 | OUT | output | Totem-pole gate drive output intended to drive a MOSFET directly, sourcing and sinking up to 1 A peak and held low when VDD is below the turn-on threshold. |
| 7 | VDD | power_in | Analog controller bias supply input, with absolute maximum 30 V, requiring a 0.1 µF ceramic bypass capacitor connected directly to GND and an absolute maximum of 30 V that must not be exceeded. |
| 8 | VREF | power_in | 5-V reference output (±1%) that must be bypassed to GND with at least 0.1 µF ceramic placed close to the pin, and must not have any external voltage above the specified VREF superimposed on it. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |

## CAD (KiCad official)

- Symbol: `UCC28C50DR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ucc28c50dr-etched.step` / `ucc28c50dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ucc28c50dr.step` / `ucc28c50dr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/ucc28c50.pdf) (58 pp, sha256 `d9b2cab289f0aa82`, retrieved 2026-10-08, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ucc28c50dr-datasheet.pdf)