# UCC28C45QDRQ1

**Texas Instruments** · AC-DC Controllers And Regulators · SOIC-8

UCC28C45QDRQ1 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier output for compensation that can both source and sink current, is internally current limited, and can be forced to GND to command zero duty cycle, with COMP sink current rated 10 mA maximum. |
| 2 | FB | input | Inverting input of the error amplifier, with the noninverting reference internally trimmed to 2.5 V ±1%. |
| 3 | CS | input | Primary-side current sense input to the PWM comparator, which terminates OUT conduction, with a typical current sense amplifier gain of 3 V/V. |
| 4 | RT/CT | bidirectional | Fixed-frequency oscillator timing pin, with timing resistor from VREF and timing capacitor to GND, where TI recommends 1 kΩ to 100 kΩ resistors and 220 pF to 4.7 nF capacitors. |
| 5 | GND | power_in | Ground return pin for the output driver stage and the logic level controller section. |
| 6 | OUT | output | Totem-pole drive output intended to directly drive a MOSFET, sourcing and sinking up to 1 A peak, actively held low when VDD is below the turn-on threshold, with output driver voltage limited to 20 V absolute maximum. |
| 7 | VDD | power_in | Analog controller bias supply input with a 20 V absolute maximum, requiring a bypass capacitor typically 0.1 µF connected directly to GND. |
| 8 | VREF | power_out | 5-V reference output with ±1% tolerance, requiring a minimum 0.1 µF ceramic bypass to GND placed as close to the pin as possible. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VREF voltage, initial accuracy | VVREF | 4.9 | 5 | 5.1 | V | IOUT = 1 mA | 5 |
| Line regulation |  |  | 0.2 | 20 | mV | VVDD = 12 V to 18 V | 5 |
| Load regulation |  |  | 3 | 25 | mV | 1 mA to 20 mA | 5 |
| Temperature stability (VREF) |  |  | 0.2 | 0.4 | mV/°C | See (2) | 5 |
| Total output variation |  | 4.82 |  | 5.18 | V | See (2) | 5 |
| Long term stability |  |  | 5 | 25 | mV | 1000 hours, TJ = 125°C, see (2) | 5 |
| Output short circuit (source current) | IVREF | 30 | 45 | 55 | mA |  | 5 |
| Initial accuracy (oscillator frequency) | fOSC | 50.5 | 53 | 55 | kHz | TJ = 25°C, see (3) | 5 |
| Initial accuracy full range (oscillator frequency) | fOSC | 50.5 |  | 57 | kHz | TJ = Full Range, see (3) | 5 |
| Voltage stability |  |  | 0.2 | 1 | % | 12 V ≤ VVDD ≤ 18 V | 5 |
| Temperature stability (oscillator) |  |  | 1 | 2.5 | % | TJ(MIN) to TJ(MAX), see (2) | 5 |
| Discharge current |  | 7.7 | 8.4 | 9 | mA | TJ = 25°C, VRT/CT = 2 V, see (4) | 5 |
| Discharge current full range |  | 7.2 | 8.4 | 9.5 | mA | TJ = Full Range, VRT/CT = 2 V, see (4) | 5 |
| Feedback input voltage, initial accuracy | VFB | 2.475 | 2.5 | 2.525 | V | TJ = 25°C, VCOMP = 2.5 V | 5 |
| Feedback input voltage, total variation | VFB | 2.45 | 2.5 | 2.55 | V | TJ = Full Range, VCOMP = 2.5 V | 5 |
| Input bias current (source current) | IFB |  | 0.1 | 2 | µA | VFB = 5 V | 5 |
| Open-loop voltage gain | AVOL | 65 | 90 |  | dB | 2 V ≤ VOUT ≤ 4 V | 5 |
| Unity gain bandwidth |  |  | 1 | 1.5 | MHz | See (2) | 5 |
| Power supply rejection ratio (error amplifier) | PSRR | 60 |  |  | dB | 12 V ≤ VVDD ≤ 18 V | 5 |
| Output sink current |  | 2 |  | 14 | mA | VFB = 2.7 V, VCOMP = 1.1 V | 5 |
| Output source current |  | 0.5 |  | 1 | mA | VFB = 2.3 V, VCOMP = 5 V | 5 |
| Low-level COMP voltage | VOL |  | 0.1 | 1.1 | V | VFB = 2.7 V, RCOMP = 15 kΩ COMP to VREF | 5 |
| Gain | ACS | 2.85 | 3 | 3.15 | V/V | TJ = 25°C, See (5) (6) | 6 |
| Gain full range | ACS | 2.75 | 3 | 3.15 | V/V | TJ = Full Range, See (5) (6) | 6 |
| Maximum input signal | VCS | 0.9 | 1 | 1.1 | V | VFB < 2.4 V | 6 |
| Power supply rejection ratio (current sense) | PSRR | 70 |  |  | dB | VVDD = 12 V to 18 V(2) (5) | 6 |
| Input bias current (source current) | ICS |  | 0.1 | 2 | µA |  | 6 |
| CS to output delay | tD |  | 35 | 70 | ns |  | 6 |
| RDS(on) pulldown | VOUT(low) |  | 5.5 | 15 | Ω | ISINK = 200 mA | 6 |
| RDS(on) pullup | VOUT(high) |  | 10 | 25 | Ω | ISOURCE = 200 mA | 6 |
| Rise time | tRISE |  | 25 | 50 | ns | COUT = 1 nF | 6 |
| Fall time | tFALL |  | 20 | 40 | ns | COUT = 1 nF | 6 |
| Start threshold (UCC28C43-Q1, UCC28C45-Q1) | VDDON | 7.8 | 8.4 | 9 | V | UCC28C43-Q1, UCC28C45-Q1 | 6 |
| Minimum operating voltage (UCC28C43-Q1, UCC28C45-Q1) | VDDOFF | 7 | 7.6 | 8.2 | V | UCC28C43-Q1, UCC28C45-Q1 | 6 |
| Maximum duty cycle | DMAX | 47 |  | 48 | % | UCC28C44-Q1, UCC28C45-Q1, UCC28C41-Q1, VFB < 2.4 V | 6 |
| Minimum duty cycle | DMIN | 0 |  |  | % | VFB > 2.6 V | 6 |
| Start-up current | ISTART-UP |  | 50 | 100 | µA | VVDD = VDDON, 0.5 V | 6 |
| Operating supply current | IVDD |  | 2.3 | 3 | mA | VFB = VCS = 0 V | 6 |
| Input voltage | VDD |  |  | 20 | V |  | 4 |
| Input current | IVDD |  |  | 30 | mA |  | 4 |
| Output drive current (peak) |  | -1 |  | 1 | A |  | 4 |
| Output energy (capacitive load) | EOUT |  |  | 5 | µJ |  | 4 |
| Analog input voltage |  | -0.3 |  | 6.3 | V | COMP, CS, FB, RT/CT | 4 |
| Output driver voltage | OUT | -0.3 |  | 20 | V |  | 4 |
| Reference voltage | VREF |  |  | 7 | V |  | 4 |
| Error amplifier output sink current |  |  |  | 10 | mA | COMP | 4 |
| Lead temperature (soldering, 10 s) | TLEAD |  |  | 300 | °C |  | 4 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 4 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 4 |
| Input voltage | VVDD |  |  | 18 | V |  | 4 |
| Output driver voltage | VOUT |  |  | 18 | V |  | 4 |
| Maximum continuous voltage from external circuitry | VREF |  |  | 5.5 | V |  | 4 |
| Average output driver current | IOUT |  |  | 200 | mA |  | 4 |
| Reference output current | IOUT(VREF) | -20 |  |  | mA |  | 4 |
| Operating ambient temperature | TA | -40 |  | 125 | °C | UCC28C4x-Q1 | 4 |
| Operating junction temperature | TJ | -40 |  | 150 | °C | UCC28C4x-Q1 | 4 |
| Junction-to-ambient thermal resistance | RθJA |  | 128.9 |  | °C/W | D (SOIC) 8 pins | 5 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 71.7 |  | °C/W | D (SOIC) 8 pins | 5 |
| Junction-to-board thermal resistance | RθJB |  | 72.3 |  | °C/W | D (SOIC) 8 pins | 5 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts |  | tin | The inductor rising slope (Sn) at the CS pin is calculated with Equation 34. Sn = | 30 |

## CAD (KiCad official)

- Symbol: `UCC28C45QDRQ1`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ucc28c45qdrq1-etched.step` / `ucc28c45qdrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ucc28c45qdrq1.step` / `ucc28c45qdrq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/ucc28c45-q1.pdf) (48 pp, sha256 `6ee1ce978e7042db`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ucc28c45qdrq1-datasheet.pdf)