component
UCC28C44QDRQ1
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownUCC28C44QDRQ1
Texas Instruments · AC-DC Controllers And Regulators · SOIC-8
UCC28C44QDRQ1 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier output for loop compensation, internally current limited so zero duty cycle can be commanded by forcing COMP to GND, and it can also serve as a control port across an opto-isolator. |
| 2 | FB | input | Inverting input of the error amplifier used for voltage-feedback loop stability, with the non-inverting input internally trimmed to 2.5 V ±1%. |
| 3 | CS | input | Primary-side current sense input to the PWM comparator that terminates OUT conduction, with a typical current sense amplifier gain of 3 V/V and an RC filter that may be required to prevent leading-edge false triggering. |
| 4 | RT/CT | bidirectional | Oscillator timing pin where a resistor from VREF sets the charging current and a capacitor to GND sets the frequency, with TI recommending timing resistors of 1 kΩ to 100 kΩ and timing capacitors of 220 pF to 4.7 nF. |
| 5 | GND | power_in | Ground return for the output driver stage and the logic-level controller section, which should be kept separate from the high-current gate driver return path. |
| 6 | OUT | output | Totem-pole gate drive output that directly drives a MOSFET with up to ±1 A peak current, and on the UCC28C44-Q1 its frequency is one-half the oscillator frequency so the duty cycle is limited to below 50%. |
| 7 | VDD | power_in | Analog controller bias supply input with an absolute maximum of 20 V and no internal clamp, requiring a ceramic bypass capacitor (typically 0.1 µF) connected directly to GND. |
| 8 | VREF | power_in | 5-V reference output (±1% tolerance) that supplies oscillator timing current and the logic supply, requiring at least 0.1 µF ceramic bypass to GND and not to be pulled to ground to stop switching. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
UCC28C44QDRQ1 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ucc28c44qdrq1-etched.step/ucc28c44qdrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucc28c44qdrq1.step/ucc28c44qdrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (49 pp, sha256
0ab76ce5a6cf1522, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).