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Contents

README

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UCC2897ARGPR

Texas Instruments · AC-DC Controllers And Regulators · QFN-20-EP(4x4)

UCC2897ARGPR from Texas Instruments, in a QFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RON passive Resistor to GND that programs the charge current and switching frequency of the internal timing capacitor.
2 ROFF passive Resistor to GND that programs the discharge current, switching frequency, and maximum duty cycle.
3 VREF power_out 5V reference voltage output that supplies up to 5 mA and is bypassed to GND with 0.1µF capacitor.
4 SYNC bidirectional Bidirectional synchronization input where external clock must exceed free-running frequency and pulse width must remain less than (1-DMAX)×TSYNC.
5 GND power_in Analog ground reference connected externally to PGND at a single point only.
6 CS input Current sense input for peak current-mode control; cycle-by-cycle current limiting activates at approximately 0.5V threshold; requires RC filter between current-sense resistor and this pin.
7 RSLOPE passive Resistor to GND that programs the slope compensation current amplitude during the main switch on-time.
8 FB input Feedback input that brings error signal from external optocoupler or error amplifier; control voltage range 2.5V to 4.5V with values below 2.5V producing zero duty-cycle output.
9 SS/SD input Soft-start and shutdown input where external capacitor is charged during soft-start and discharged during shutdown.
10 PGND power_in Power ground return for high-current gate driver outputs OUT and AUX; should be connected with minimal impedance and loop area.
11 AUX output Auxiliary P-channel gate driver output providing 2A source and 2A sink current for active-clamp switching with active-low logic.
12 OUT output Main N-channel gate driver output providing 2A source and 2A sink current with active-high logic; 10kΩ pull-down resistor to PGND recommended.
13 PVDD power_in Isolated power supply input for the gate driver circuits separated from VDD internally.
14 VDD power_in Main power supply input requiring 1µF bypass capacitor and energy storage capacitor for proper soft-start operation.
15 LINEUV input Line undervoltage monitor with 1.27V threshold; hysteresis programmed by external resistor divider at LINEUV pin.
16 LINEOV input Line overvoltage monitor with 1.27V threshold; hysteresis programmed by external resistor divider at LINEOV pin.
17 N/C unconnected No internal connection; pin must be left unconnected.
18 VIN power_in Input power rail with internal high-voltage JFET start-up device rated to 120V maximum input voltage.
19 N/C unconnected No internal connection; pin must be left unconnected.
20 RDEL passive Resistor to GND that programs the turn-on delay between AUX and OUT gate driver outputs.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-20-EP(4x4)
Category Power Management (PMIC)
Pins 21

CAD (KiCad official)

  • Symbol: UCC2897ARGPR
  • Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
  • 3D model: QFN-20-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: ucc2897argpr-etched.step / ucc2897argpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc2897argpr.step / ucc2897argpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (50 pp, sha256 fb294981fe94b45c, retrieved 2026-09-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF