UCC28910DR from Texas Instruments, in a SOIC-7. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND	power_in	Ground pin is the reference for the controller and the low-side return for the drive output, and AC decoupling should return as close as possible to this pin.
2	GND	power_in	Ground pin is the reference for the controller and the low-side return for the drive output, shorted together with the other GND pins to pull out FET heat.
3	GND	power_in	Ground pin is the reference for the controller and the low-side return for the drive output, shorted together with the other GND pins to pull out FET heat.
4	IPK	output	A resistor RIPK from IPK to GND sets the maximum power FET peak current, and a short to GND selects the internal 600 mA peak for UCC28910.
5	VS	power_in	Voltage Sense pin receives a divider from the auxiliary winding for output voltage and timing feedback, with the line-sense enable threshold at 210 μA and disable threshold at 75 μA.
6	VDD	power_in	Controller supply with VDD turn-on UVLO of 9.5 V and turn-off of 6.5 V, operating up to 26 V (VDDCLAMP minimum) and clamp current limited to 10 mA.
8	DRAIN	power_in	Drain of the internal 700-V power FET, which also supplies the high-voltage start-up current source, with a maximum DRAIN voltage of 700 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-7
Category	Power Management (PMIC)
Pins	7

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
DRAIN voltage	VDRAIN			700	V		7
Negative drain current	IDRAIN	-100			mA		7
Maximum VDD clamp current	IVDD(clp)			10	mA		7
VS voltage range	VVS			7	V		7
VIPK voltage range	VIPK	-0.5		5	V		7
Peak VS pin current (current out of the pin)	IVS	-1.2			mA		7
Pulsed drain current, UCC28910	IDRAIN			950	mA	Maximum pulse width = 100 μs	7
Lead temperature	TLEAD			260	°C	1.6 mm (1/16 inch) from case for 10 seconds	7
Operating junction temperature range	TJ	-55		150	°C		7
Storage temperature	Tstg	-65		150	°C		7
Current out of the terminal	IVS			1	mA		7
Maximum drain peak current, UCC28910	ID(peak_max)			600	mA	UCC28910	7
Operating junction temperature	TJ	-40		125	°C		8
Supply current, run	IRUN	2.3	2.9	3.4	mA	VVS = 3.9 V, fSW = fSW(max)	8
Quiescent supply current	IRUNQ	1.9	2.35	2.8	mA	VVS = 3.9 V, fSW = 0 Hz	8
Wait supply current	IWAIT	270		370	µA	VVS = 4.1 V, fSW = fSW(min), TJ = 25°C	8
Quiescent wait supply current	IWAITQ	200		280	µA	VVS = 4.1 V, fSW = 0 Hz, TJ = 25°C	8
Supply current before start	ISTART	65		90	µA	0 V ≤ VVDD ≤ 5.6 V, VDRAIN = 0 V	8
Supply current after fault	IFAULT	190		260	µA	fSW = 0 Hz	8
VDD turn-on threshold	VDDON	9	9.5	10	V	VVDD low to high	8
VDD turn-off threshold	VDDOFF	6	6.5	7	V	VVDD high to low	8
HV current source start	VDDHV(on)	4.8	5.2	5.6	V	VVDD high to low	8
UVLO hysteresis	ΔVUVLO	2.8	3	3.2	V	VDDON, VDDOFF	8
Startup current with VDD shorted to GND	ICH1	-300		-100	µA	VVDD < 250 mV, VDRAIN = 100 V	8
Sourced current for startup at high VDD	ICH2	-9.75		-0.4	mA	VVDD = 8 V, VDRAIN = 100 V	8
Sourced current for startup at low VDD	ICH3	-13.75		-1.3	mA	VVDD = 2 V, VDRAIN = 100 V	8
Regulating level	VVSR	4.01	4.05	4.09	V	Measured in no load condition, TJ = 25°C	9
Negative clamp level	VVSNC	-325	-250	-190	mV	IVS = -300 μA	9
Input bias current	IVS	-0.25	0	0.25	µA	VVS = 4 V	9
Over-voltage threshold	VOVP	4.45	4.6	4.75	V	At VS input, TJ = 25°C	9
VS line sense run current	IVSL(run)	175	215	260	µA	Current out of VS pin, increasing	9
VS line sense stop current	IVSL(stop)	60	75	100	µA	Current out of VS pin, decreasing	9
Line sense IVS ratio	KVSL	2.55	2.7	2.9	A/A	IVSL(run) / IVSL(stop)	9
VDD voltage clamp	VDDCLP	26	28	30	V	IVDDCLP forced = 2 mA	9
VDD clamp over current	IVDDCLP_OC	4.65	6	7.65	mA	VVDD > 25 V	9
DRAIN over current	ID(ocp)	725	850	925	mA	IPK pin shorted to GND	9
Equivalent VCST(OCP), ID(ocp) x RIPK	VCSTE_OCP	670	770	830	V	VVS = 3.9 V	9
Maximum FET on time at high load	tONMAX(max)	13	18	24	µs	VVS < 3.9 V, IPK shorted to GND	9
Maximum FET on time at low load	tONMAX(min)	4.3	6	10	µs	VVS > 4.1 V, IPK shorted to GND	9
Power FET on resistance	RDS(on)	10.5		12	Ω	ID = 150 mA, TJ = 25°C	9
Power FET on resistance	RDS(on)	18.4		21.5	Ω	ID = 150 mA, TJ = 125°C	9
DRAIN pin leakage current	ILEAKAGE			10	µA	VDS = 400 V HV, VS = 4.2 V DC, TJ = 25°C	9
DRAIN pin leakage current	ILEAKAGE			20	µA	VDS = 400 V HV, VS = 4.2 V DC, TJ = 125°C	9
Maximum DRAIN peak current	ID_PEAK(max)	582	600	618	mA	IPK pin shorted to GND, TJ = 25°C	10
IPK to GND resistance Max to assume IPK shorted to GND	RIPK_SHORT			200	Ω		10
IPK to GND minimum resistance	RIPK(min)	900			Ω		10
Equivalent current sense threshold, ID_PK(max) × RIPK	VCSTE(max)	532	540	548	V	VVS = 3.9 V, TJ = 25°C	10
Equivalent current sense threshold, ID_PK(min) × RIPK	VCSTE(min)	160	180	200	V	VVS = 4.1 V	10
AM control ratio, VCSE(max) / VCSE(min)	KAM	2.3	3	3.5	V/V		10
CC regulation constant, VCSET(max) × KCC	VCCR	216	223	230	V	VVS < 3.9 V, TJ = 25°C	10
Maximum switching frequency	fSW(max)	105	115	125	kHz	VVS < 3.9 V	10
Minimum switching frequency	fSW(min)	360	420	490	Hz	VVS > 4.1 V	10
Zero crossing timeout delay	tZTO	1.8	2.1	2.65	µs	VVS < 3.9 V	10
Junction-to-ambient thermal resistance	θJA		102.2		°C/W		8
Junction-to-case (top) thermal resistance	θJCtop		39.1		°C/W		8
Junction-to-board thermal resistance	θJB		54.7		°C/W		8
Junction-to-top characterization parameter	ψJT		5.4		°C/W		8
Junction-to-board characterization parameter	ψJB		54.7		°C/W		8

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts	copper		(3) Maximum continuous power with open frame design at 50°C ambient, with adequate copper area connected on GND pin and /or	3

CAD (KiCad official)

Symbol: UCC28910DR
Footprint: Package_SO:SOIC-8-N7_3.9x4.9mm_P1.27mm
3D model: SOIC-7 (KiCad packages3D, STEP)
3D model files: ucc28910dr-etched.step / ucc28910dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc28910dr.step / ucc28910dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (56 pp, sha256 cdddf8860e8cc978, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

UCC28910DR

Verified UCC28910DR

Verification log 1 record

3D Model

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