component
UCC28782ADRTWR
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, WQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"slug": "ucc28782adrtwr",
"title": "UCC28782ADRTWR",
"brief": "Texas Instruments AC-DC Controllers And Regulators, WQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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"manufacturer": "Texas Instruments",
"package": "WQFN-24(4x4)",
"pin_count": 25,
"category": "Power Management (PMIC)",
"subcategory": "AC-DC Controllers And Regulators",
"datasheet": "https://www.ti.com/cn/lit/gpn/ucc28782",
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"digikey": "296-UCC28782ADRTWRTR-ND",
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"pins": [
{
"number": "1",
"name": "FLT",
"type": "input",
"description": "The controller enters the fault state if FLT is pulled above 4.5 V or below 0.5 V, with a 50-µA source for an external NTC to AGND and a 750-µs line-OVP delay when used for bulk-voltage sensing."
},
{
"number": "2",
"name": "RTZ",
"type": "input",
"description": "A resistor from RTZ to AGND programs the adaptive delay from the PWMH turn-off edge to the PWML turn-on edge, with 20 kΩ < RRTZ < 1.1 MΩ recommended and parasitic capacitance minimized."
},
{
"number": "3",
"name": "RDM",
"type": "input",
"description": "A resistor from RDM to AGND programs the synthesized demagnetization time that sets the PWMH on-time for ZVS tuning, with 2 kΩ < RRDM < 500 kΩ recommended."
},
{
"number": "4",
"name": "IPC",
"type": "input",
"description": "The intelligent power control pin sources 50 µA into a resistor to AGND or CS to raise the peak-current threshold at very light load, with VIPC used to set the SBP2 current level."
},
{
"number": "5",
"name": "BUR",
"type": "input",
"description": "A resistor divider from REF to AGND sets the burst-mode threshold voltage VBUR, which must be between 0.7 V and 2.4 V to be effective."
},
{
"number": "6",
"name": "FB",
"type": "input",
"description": "The feedback current signal from the optocoupler is sensed at this pin, which presents a 4.25-V node with 0 µA to 75 µA pulled out of the pin, and a 220-pF filter to REF is recommended."
},
{
"number": "7",
"name": "REF",
"type": "power_out",
"description": "The 5-V reference output requires a 0.22-µF ceramic bypass to AGND, can supply limited external load current, and pulling it low shuts down PWM and forces a VDD restart."
},
{
"number": "8",
"name": "AGND",
"type": "power_in",
"description": "Analog ground that is the return for all analog control signals and for the PWMH and RUN drivers, and must be kept separate from noisy ground paths."
},
{
"number": "9",
"name": "CS",
"type": "input",
"description": "The current-sense input sets the peak primary current through a line-compensation resistor, and the controller enters over-current fault when CS exceeds 1.2 V."
},
{
"number": "10",
"name": "RUN",
"type": "output",
"description": "The RUN output is high in the run state to enable switching and can source up to about 44 mA peak to bias an external isolator or gate driver, and it is low during start-up, wait, and fault states."
},
{
"number": "11",
"name": "PGND",
"type": "power_in",
"description": "Low-side ground return of the PWML driver, which may be Kelvin-connected to the current-sense resistor and tolerates 5-V positive and -1-V negative transients relative to AGND."
},
{
"number": "12",
"name": "PWML",
"type": "output",
"description": "Low-side gate driver output with 0.5-A peak source and 1.9-A peak sink capability, clamped to the P13 voltage."
},
{
"number": "13",
"name": "S13",
"type": "output",
"description": "The switched 13-V rail is coupled to P13 through an internal 2.8-Ω switch controlled by RUN, and PWML switching begins only after S13 exceeds the 10-V power-good threshold."
},
{
"number": "14",
"name": "P13",
"type": "power_out",
"description": "The regulated 13-V output derived from VDD requires a 1-µF ceramic bypass to AGND, and a 20-V Zener to AGND is recommended for protection."
},
{
"number": "15",
"name": "PWMH",
"type": "output",
"description": "The PWM output drives the high-side clamp switch through an external high-voltage gate driver and is clamped to the 5-V REF level."
},
{
"number": "16",
"name": "SWS",
"type": "input",
"description": "The switch-node sensing input for ZVS auto-tuning must be coupled through a current-limiting resistor above 500 Ω, and only signals below 15 V are monitored."
},
{
"number": "17",
"name": "XCD",
"type": "input",
"description": "The X-capacitor discharge input detects AC-line zero crossings at a 6.5-V threshold and supports up to 2-mA maximum discharge current, and it must be tied to AGND if the function is not used."
},
{
"number": "18",
"name": "XCD",
"type": "input",
"description": "This redundant X-capacitor discharge input works in parallel with pin 17 so the discharge function continues if one XCD pin is in a fail-open condition."
},
{
"number": "19",
"name": "VDD",
"type": "power_in",
"description": "The controller bias input and integrated boost converter output requires a hold-up capacitor to BGND, with a 10-µF to 15-µF ceramic and a minimum 25-V rating recommended for wide-output designs."
},
{
"number": "20",
"name": "BGND",
"type": "power_in",
"description": "Boost converter return connected to the source of the internal 30-V boost switch, kept separate to minimize the high di/dt switching loop."
},
{
"number": "21",
"name": "BSW",
"type": "input",
"description": "The boost converter switch node connected to the drain of the internal 30-V boost switch has an absolute maximum rating of -0.3 V to 30 V."
},
{
"number": "22",
"name": "BIN",
"type": "input",
"description": "The boost converter input from the rectified auxiliary winding has an absolute maximum rating of -0.3 V to 30 V, and a 24-V TVS to AGND is recommended for protection."
},
{
"number": "23",
"name": "VS",
"type": "power_in",
"description": "The voltage-sense input from the auxiliary winding monitors input and output voltages and zero-current detection, with an absolute maximum range of -0.75 V to 7 V."
},
{
"number": "24",
"name": "SET",
"type": "input",
"description": "The SET pin selects GaN or Si primary-FET optimization of ZVS, dead-time and protection settings, tied to AGND for GaN (VSET = 0 V) or to REF for Si (VSET = 5 V)."
},
{
"number": "25",
"name": "EP",
"type": "power_in",
"description": "The exposed thermal pad must be connected to AGND."
}
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],
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"at": "2026-10-21T01:05:32"
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"Package": "WQFN-24(4x4)",
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"appearance": {
"contacts": {
"quote": "in order to minimize the regulator output switching loop area. Rather than with the BGND pin, the low-noise ground terminal of CVDD should be used to connect the BGND net to the AGND pin with a low im",
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"doc": "ds.pdf",
"material": "copper"
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{
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{
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{
"name": "Supply current, start state",
"symbol": "ISTART",
"kind": "electrical",
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"typ": 235,
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"conditions": "VVDD = VVDD(ON) - 100 mV, VVS = 0 V",
"source_page": 10,
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{
"name": "VDD startup current limit during startup",
"symbol": "IVDD(LIMIT)",
"kind": "electrical",
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"typ": 2,
"max": 2.53,
"conditions": "VVDD increasing, VSWS - VVDD = 1 V, VVDD = 16.5 V",
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"min": 16.31,
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"conditions": "VVDD increasing",
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"min": 9.94,
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{
"name": "VDD regulation level in boost mode",
"symbol": "VVDD(BOOST)",
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"conditions": "IVDD = 0 mA to 30 mA, VBIN = 9 V",
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{
"name": "UVLO on voltage of VBIN in boost mode",
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