UCC28782ADRTWR

Texas Instruments · AC-DC Controllers And Regulators · WQFN-24(4x4)

UCC28782ADRTWR from Texas Instruments, in a WQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	FLT	input	The controller enters the fault state if FLT is pulled above 4.5 V or below 0.5 V, with a 50-µA source for an external NTC to AGND and a 750-µs line-OVP delay when used for bulk-voltage sensing.
2	RTZ	input	A resistor from RTZ to AGND programs the adaptive delay from the PWMH turn-off edge to the PWML turn-on edge, with 20 kΩ < RRTZ < 1.1 MΩ recommended and parasitic capacitance minimized.
3	RDM	input	A resistor from RDM to AGND programs the synthesized demagnetization time that sets the PWMH on-time for ZVS tuning, with 2 kΩ < RRDM < 500 kΩ recommended.
4	IPC	input	The intelligent power control pin sources 50 µA into a resistor to AGND or CS to raise the peak-current threshold at very light load, with VIPC used to set the SBP2 current level.
5	BUR	input	A resistor divider from REF to AGND sets the burst-mode threshold voltage VBUR, which must be between 0.7 V and 2.4 V to be effective.
6	FB	input	The feedback current signal from the optocoupler is sensed at this pin, which presents a 4.25-V node with 0 µA to 75 µA pulled out of the pin, and a 220-pF filter to REF is recommended.
7	REF	power_out	The 5-V reference output requires a 0.22-µF ceramic bypass to AGND, can supply limited external load current, and pulling it low shuts down PWM and forces a VDD restart.
8	AGND	power_in	Analog ground that is the return for all analog control signals and for the PWMH and RUN drivers, and must be kept separate from noisy ground paths.
9	CS	input	The current-sense input sets the peak primary current through a line-compensation resistor, and the controller enters over-current fault when CS exceeds 1.2 V.
10	RUN	output	The RUN output is high in the run state to enable switching and can source up to about 44 mA peak to bias an external isolator or gate driver, and it is low during start-up, wait, and fault states.
11	PGND	power_in	Low-side ground return of the PWML driver, which may be Kelvin-connected to the current-sense resistor and tolerates 5-V positive and -1-V negative transients relative to AGND.
12	PWML	output	Low-side gate driver output with 0.5-A peak source and 1.9-A peak sink capability, clamped to the P13 voltage.
13	S13	output	The switched 13-V rail is coupled to P13 through an internal 2.8-Ω switch controlled by RUN, and PWML switching begins only after S13 exceeds the 10-V power-good threshold.
14	P13	power_out	The regulated 13-V output derived from VDD requires a 1-µF ceramic bypass to AGND, and a 20-V Zener to AGND is recommended for protection.
15	PWMH	output	The PWM output drives the high-side clamp switch through an external high-voltage gate driver and is clamped to the 5-V REF level.
16	SWS	input	The switch-node sensing input for ZVS auto-tuning must be coupled through a current-limiting resistor above 500 Ω, and only signals below 15 V are monitored.
17	XCD	input	The X-capacitor discharge input detects AC-line zero crossings at a 6.5-V threshold and supports up to 2-mA maximum discharge current, and it must be tied to AGND if the function is not used.
18	XCD	input	This redundant X-capacitor discharge input works in parallel with pin 17 so the discharge function continues if one XCD pin is in a fail-open condition.
19	VDD	power_in	The controller bias input and integrated boost converter output requires a hold-up capacitor to BGND, with a 10-µF to 15-µF ceramic and a minimum 25-V rating recommended for wide-output designs.
20	BGND	power_in	Boost converter return connected to the source of the internal 30-V boost switch, kept separate to minimize the high di/dt switching loop.
21	BSW	input	The boost converter switch node connected to the drain of the internal 30-V boost switch has an absolute maximum rating of -0.3 V to 30 V.
22	BIN	input	The boost converter input from the rectified auxiliary winding has an absolute maximum rating of -0.3 V to 30 V, and a 24-V TVS to AGND is recommended for protection.
23	VS	power_in	The voltage-sense input from the auxiliary winding monitors input and output voltages and zero-current detection, with an absolute maximum range of -0.75 V to 7 V.
24	SET	input	The SET pin selects GaN or Si primary-FET optimization of ZVS, dead-time and protection settings, tied to AGND for GaN (VSET = 0 V) or to REF for Si (VSET = 5 V).
25	EP	power_in	The exposed thermal pad must be connected to AGND.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WQFN-24(4x4)
Category	Power Management (PMIC)
Pins	25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input voltage, VDD	VDD			38	V		9
Input voltage, VDD-SWS		-20		38	V		9
Input voltage, SWS	SWS	-6		38	V		9
Input voltage, CS	CS	-0.3		3.6	V		9
Input voltage, VS	VS	-0.75		7	V		9
Input voltage, PGND	PGND	-1		4	V		9
Input voltage, RTZ, BUR, SET, RDM, IPC, FLT, FB		-0.3		7	V		9
Input voltage, XCD, BIN, BSW		-0.3		30	V		9
Output voltage, REF, PWMH, RUN		-0.3		7	V		9
Output voltage, P13, S13, PWML		-0.3		20	V		9
Operating junction temperature	TJ	-40		150	°C		9
Storage temperature	Tstg	-65		150	°C		9
Bias supply operating voltage	VVDD	14		34	V		10
VDD capacitor	CVDD	10			µF		10
P13 bypass capacitor	CP13	1			µF		10
REF bypass capacitor	CREF	0.22			µF		10
Operating junction temperature	TJ	-40		140	°C		10
Junction-to-ambient thermal resistance	RθJA		43.1		°C/W		10
Junction-to-case (top) thermal resistance	RθJC(top)		31.6		°C/W		10
Junction-to-board thermal resistance	RθJB		20.3		°C/W		10
Junction-to-top characterization parameter	ΨJT		0.5		°C/W		10
Junction-to-board characterization parameter	ΨJB		20.3		°C/W		10
Junction-to-case (bottom) thermal resistance	RθJC(bot)		5.7		°C/W		10
Supply current, run state (no switching)	IRUN(STOP)	0.88	2.2	2.66	mA	No switching	10
Supply current, run state (switching)	IRUN(SW)	2.66	3	3.55	mA	Switching, IVSL = 0 µA	10
Supply current, wait state	IWAIT	452	580	695	µA	IFB = -85 µA, VBIN = VBSW = VVDD = 20 V, sum of IBIN, IBSW, and IVDD	10
Supply current, start state	ISTART	150	235	301	µA	VVDD = VVDD(ON) - 100 mV, VVS = 0 V	10
VDD startup current limit during startup	IVDD(LIMIT)	1.2	2	2.53	mA	VVDD increasing, VSWS - VVDD = 1 V, VVDD = 16.5 V	10
VDD turnon threshold	VVDD(ON)	16.31	17	17.91	V	VVDD increasing	10
VDD turnoff threshold	VVDD(OFF)	9.94	10.6	11.17	V	VVDD decreasing	10
VDD regulation level in boost mode	VVDD(BOOST)	17.6	18.5	19.4	V	IVDD = 0 mA to 30 mA, VBIN = 9 V	11
UVLO on voltage of VBIN in boost mode	VBIN(ON)	2.03	2.2	2.42	V	VBIN increasing	11
Highest VBIN to enable boost mode	VBIN(EN)	14.44	14.9	15.47	V	VBIN decreasing	11
Peak current threshold in CPC control	IBSW(MAX)	0.27	0.335	0.38	A		11
Maximum switching frequency in CPC control (UCC28782AD, UCC28782BDL, UCC28782CD)	fBSW	389	420	499	kHz	VBIN = 9 V	11
Minimum off time in COT control	tBOFF(MIN)	198	255	353	ns	IFB = -85 µA	11
P13 voltage level including load regulation	VP13	12	12.8	13.6	V	0 mA to 60 mA out of P13, run state, VVDD = 20 V	11
REF voltage level	VREF	4.9	5	5.13	V	IREF = 0 A	11
Current sourcing limit of REF pin	IREF(MAX)	14.3	17	20.3	mA	REF shorted to AGND, VVDD = 20 V	11
S13_OK threshold to enable switching	VS13_OK	9.63	10.2	10.7	V	VRUN = 5 V	11
Regulated FB voltage level	VFB(REG)	4.02	4.25	4.53	V		15
Maximum control FB current	IFB(SBP)	64.2	75	87.1	µA	IFB increasing	15
VS line-sense run current	IVSL(RUN)	313	365	408.6	µA	Current out of VS pin increasing	14
Shut-down voltage of VVDD for boost output OVP	VBOVPTH	21.5	25	28.2	V		14
Brown-out detection delay time	tBO	28.8	55	85.2	ms	IVSL < IVSL(STOP)	14
OPP fault timer (UCC28782AD, UCC28782BDL, UCC28782CD)	tOPP	130	164	201.1	ms	IFB = 0 A	14
Fault reset delay timer (UCC28782AD, UCC28782BDL, UCC28782CD)	tFDR	1.2	1.5	2.25	s	OCP, OPP, OVP, SCP or CS pin fault	14
Maximum PWML on-time for detecting CS pin fault (VSET = 5 V)	tCSF1	1.6	2.05	2.5	µs	VSET = 5 V	14
Maximum PWML on-time for detecting CS pin fault (VSET = 0 V)	tCSF0	0.85	1.05	1.27	µs	RRDM < RRDM(TH) for VSET = 0 V	14
RRDM threshold for CS pin fault	RRDM(TH)	35	55	70	kΩ		14
Shut-down voltage of input OVP	VIOVPTH	4.3	4.5	4.67	V	FLT voltage increasing	14
NTC shut-down voltage	VNTCTH	0.47	0.5	0.52	V	FLT voltage decreasing	14
SWS zero voltage threshold (VSET = 0 V)	VTH(SWS)	3.7	4.04	4.4	V	VSET = 0 V	14
SWS zero voltage threshold (VSET = 5 V)	VTH(SWS)	8.1	8.5	9.1	V	VSET = 5 V	14
Maximum programmable dead time from PWMH low to PWML high	tZ(MAX)	397.8	478	592.8	ns	RRTZ = 280 kΩ, IVSL = -1 mA, VSET = 5 V	14
Maximum PWMH width with maximum tuning (UCC28782AD, UCC28782BDL, UCC28782CD)	tDM(MAX)	6	6.95	7.53	µs	VSWS = 12 V	15
Minimum PWMH width with minimum tuning (UCC28782AD, UCC28782BDL, UCC28782CD)	tDM(MIN)	3	3.43	3.77	µs	VSWS = 0 V	15
Clamping voltage for XCD OVP	VXCD(OVP)	23	26	30	V	IXCD = 20 mA	15
Maximum XCD discharge current	IXCD(MAX)	1.65	2	2.5	mA	VXCD = 15 V	15
Dwell time for each XCD sense step (UCC28782AD, UCC28782BDL, UCC28782CD)	tXCD(STEP)	9	12	14	ms		15

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts	copper		to minimize the regulator output switching loop area. Rather than with the BGND pin, the low-noise ground terminal of CVDD should be used to connect the BGND net to the AGND pin with a low im	36

CAD (KiCad official)

Symbol: UCC28782ADRTWR
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
3D model: WQFN-24(4x4) (KiCad packages3D, STEP)
3D model files: ucc28782adrtwr-etched.step / ucc28782adrtwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc28782adrtwr.step / ucc28782adrtwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (100 pp, sha256 8ad1796404544817, retrieved 2026-10-21, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# UCC28782ADRTWR

**Texas Instruments** · AC-DC Controllers And Regulators · WQFN-24(4x4)

UCC28782ADRTWR from Texas Instruments, in a WQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FLT | input | The controller enters the fault state if FLT is pulled above 4.5 V or below 0.5 V, with a 50-µA source for an external NTC to AGND and a 750-µs line-OVP delay when used for bulk-voltage sensing. |
| 2 | RTZ | input | A resistor from RTZ to AGND programs the adaptive delay from the PWMH turn-off edge to the PWML turn-on edge, with 20 kΩ < RRTZ < 1.1 MΩ recommended and parasitic capacitance minimized. |
| 3 | RDM | input | A resistor from RDM to AGND programs the synthesized demagnetization time that sets the PWMH on-time for ZVS tuning, with 2 kΩ < RRDM < 500 kΩ recommended. |
| 4 | IPC | input | The intelligent power control pin sources 50 µA into a resistor to AGND or CS to raise the peak-current threshold at very light load, with VIPC used to set the SBP2 current level. |
| 5 | BUR | input | A resistor divider from REF to AGND sets the burst-mode threshold voltage VBUR, which must be between 0.7 V and 2.4 V to be effective. |
| 6 | FB | input | The feedback current signal from the optocoupler is sensed at this pin, which presents a 4.25-V node with 0 µA to 75 µA pulled out of the pin, and a 220-pF filter to REF is recommended. |
| 7 | REF | power_out | The 5-V reference output requires a 0.22-µF ceramic bypass to AGND, can supply limited external load current, and pulling it low shuts down PWM and forces a VDD restart. |
| 8 | AGND | power_in | Analog ground that is the return for all analog control signals and for the PWMH and RUN drivers, and must be kept separate from noisy ground paths. |
| 9 | CS | input | The current-sense input sets the peak primary current through a line-compensation resistor, and the controller enters over-current fault when CS exceeds 1.2 V. |
| 10 | RUN | output | The RUN output is high in the run state to enable switching and can source up to about 44 mA peak to bias an external isolator or gate driver, and it is low during start-up, wait, and fault states. |
| 11 | PGND | power_in | Low-side ground return of the PWML driver, which may be Kelvin-connected to the current-sense resistor and tolerates 5-V positive and -1-V negative transients relative to AGND. |
| 12 | PWML | output | Low-side gate driver output with 0.5-A peak source and 1.9-A peak sink capability, clamped to the P13 voltage. |
| 13 | S13 | output | The switched 13-V rail is coupled to P13 through an internal 2.8-Ω switch controlled by RUN, and PWML switching begins only after S13 exceeds the 10-V power-good threshold. |
| 14 | P13 | power_out | The regulated 13-V output derived from VDD requires a 1-µF ceramic bypass to AGND, and a 20-V Zener to AGND is recommended for protection. |
| 15 | PWMH | output | The PWM output drives the high-side clamp switch through an external high-voltage gate driver and is clamped to the 5-V REF level. |
| 16 | SWS | input | The switch-node sensing input for ZVS auto-tuning must be coupled through a current-limiting resistor above 500 Ω, and only signals below 15 V are monitored. |
| 17 | XCD | input | The X-capacitor discharge input detects AC-line zero crossings at a 6.5-V threshold and supports up to 2-mA maximum discharge current, and it must be tied to AGND if the function is not used. |
| 18 | XCD | input | This redundant X-capacitor discharge input works in parallel with pin 17 so the discharge function continues if one XCD pin is in a fail-open condition. |
| 19 | VDD | power_in | The controller bias input and integrated boost converter output requires a hold-up capacitor to BGND, with a 10-µF to 15-µF ceramic and a minimum 25-V rating recommended for wide-output designs. |
| 20 | BGND | power_in | Boost converter return connected to the source of the internal 30-V boost switch, kept separate to minimize the high di/dt switching loop. |
| 21 | BSW | input | The boost converter switch node connected to the drain of the internal 30-V boost switch has an absolute maximum rating of -0.3 V to 30 V. |
| 22 | BIN | input | The boost converter input from the rectified auxiliary winding has an absolute maximum rating of -0.3 V to 30 V, and a 24-V TVS to AGND is recommended for protection. |
| 23 | VS | power_in | The voltage-sense input from the auxiliary winding monitors input and output voltages and zero-current detection, with an absolute maximum range of -0.75 V to 7 V. |
| 24 | SET | input | The SET pin selects GaN or Si primary-FET optimization of ZVS, dead-time and protection settings, tied to AGND for GaN (VSET = 0 V) or to REF for Si (VSET = 5 V). |
| 25 | EP | power_in | The exposed thermal pad must be connected to AGND. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-24(4x4) |
| Category | Power Management (PMIC) |
| Pins | 25 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage, VDD | VDD |  |  | 38 | V |  | 9 |
| Input voltage, VDD-SWS |  | -20 |  | 38 | V |  | 9 |
| Input voltage, SWS | SWS | -6 |  | 38 | V |  | 9 |
| Input voltage, CS | CS | -0.3 |  | 3.6 | V |  | 9 |
| Input voltage, VS | VS | -0.75 |  | 7 | V |  | 9 |
| Input voltage, PGND | PGND | -1 |  | 4 | V |  | 9 |
| Input voltage, RTZ, BUR, SET, RDM, IPC, FLT, FB |  | -0.3 |  | 7 | V |  | 9 |
| Input voltage, XCD, BIN, BSW |  | -0.3 |  | 30 | V |  | 9 |
| Output voltage, REF, PWMH, RUN |  | -0.3 |  | 7 | V |  | 9 |
| Output voltage, P13, S13, PWML |  | -0.3 |  | 20 | V |  | 9 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 9 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 9 |
| Bias supply operating voltage | VVDD | 14 |  | 34 | V |  | 10 |
| VDD capacitor | CVDD | 10 |  |  | µF |  | 10 |
| P13 bypass capacitor | CP13 | 1 |  |  | µF |  | 10 |
| REF bypass capacitor | CREF | 0.22 |  |  | µF |  | 10 |
| Operating junction temperature | TJ | -40 |  | 140 | °C |  | 10 |
| Junction-to-ambient thermal resistance | RθJA |  | 43.1 |  | °C/W |  | 10 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 31.6 |  | °C/W |  | 10 |
| Junction-to-board thermal resistance | RθJB |  | 20.3 |  | °C/W |  | 10 |
| Junction-to-top characterization parameter | ΨJT |  | 0.5 |  | °C/W |  | 10 |
| Junction-to-board characterization parameter | ΨJB |  | 20.3 |  | °C/W |  | 10 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) |  | 5.7 |  | °C/W |  | 10 |
| Supply current, run state (no switching) | IRUN(STOP) | 0.88 | 2.2 | 2.66 | mA | No switching | 10 |
| Supply current, run state (switching) | IRUN(SW) | 2.66 | 3 | 3.55 | mA | Switching, IVSL = 0 µA | 10 |
| Supply current, wait state | IWAIT | 452 | 580 | 695 | µA | IFB = -85 µA, VBIN = VBSW = VVDD = 20 V, sum of IBIN, IBSW, and IVDD | 10 |
| Supply current, start state | ISTART | 150 | 235 | 301 | µA | VVDD = VVDD(ON) - 100 mV, VVS = 0 V | 10 |
| VDD startup current limit during startup | IVDD(LIMIT) | 1.2 | 2 | 2.53 | mA | VVDD increasing, VSWS - VVDD = 1 V, VVDD = 16.5 V | 10 |
| VDD turnon threshold | VVDD(ON) | 16.31 | 17 | 17.91 | V | VVDD increasing | 10 |
| VDD turnoff threshold | VVDD(OFF) | 9.94 | 10.6 | 11.17 | V | VVDD decreasing | 10 |
| VDD regulation level in boost mode | VVDD(BOOST) | 17.6 | 18.5 | 19.4 | V | IVDD = 0 mA to 30 mA, VBIN = 9 V | 11 |
| UVLO on voltage of VBIN in boost mode | VBIN(ON) | 2.03 | 2.2 | 2.42 | V | VBIN increasing | 11 |
| Highest VBIN to enable boost mode | VBIN(EN) | 14.44 | 14.9 | 15.47 | V | VBIN decreasing | 11 |
| Peak current threshold in CPC control | IBSW(MAX) | 0.27 | 0.335 | 0.38 | A |  | 11 |
| Maximum switching frequency in CPC control (UCC28782AD, UCC28782BDL, UCC28782CD) | fBSW | 389 | 420 | 499 | kHz | VBIN = 9 V | 11 |
| Minimum off time in COT control | tBOFF(MIN) | 198 | 255 | 353 | ns | IFB = -85 µA | 11 |
| P13 voltage level including load regulation | VP13 | 12 | 12.8 | 13.6 | V | 0 mA to 60 mA out of P13, run state, VVDD = 20 V | 11 |
| REF voltage level | VREF | 4.9 | 5 | 5.13 | V | IREF = 0 A | 11 |
| Current sourcing limit of REF pin | IREF(MAX) | 14.3 | 17 | 20.3 | mA | REF shorted to AGND, VVDD = 20 V | 11 |
| S13_OK threshold to enable switching | VS13_OK | 9.63 | 10.2 | 10.7 | V | VRUN = 5 V | 11 |
| Regulated FB voltage level | VFB(REG) | 4.02 | 4.25 | 4.53 | V |  | 15 |
| Maximum control FB current | IFB(SBP) | 64.2 | 75 | 87.1 | µA | IFB increasing | 15 |
| VS line-sense run current | IVSL(RUN) | 313 | 365 | 408.6 | µA | Current out of VS pin increasing | 14 |
| Shut-down voltage of VVDD for boost output OVP | VBOVPTH | 21.5 | 25 | 28.2 | V |  | 14 |
| Brown-out detection delay time | tBO | 28.8 | 55 | 85.2 | ms | IVSL < IVSL(STOP) | 14 |
| OPP fault timer (UCC28782AD, UCC28782BDL, UCC28782CD) | tOPP | 130 | 164 | 201.1 | ms | IFB = 0 A | 14 |
| Fault reset delay timer (UCC28782AD, UCC28782BDL, UCC28782CD) | tFDR | 1.2 | 1.5 | 2.25 | s | OCP, OPP, OVP, SCP or CS pin fault | 14 |
| Maximum PWML on-time for detecting CS pin fault (VSET = 5 V) | tCSF1 | 1.6 | 2.05 | 2.5 | µs | VSET = 5 V | 14 |
| Maximum PWML on-time for detecting CS pin fault (VSET = 0 V) | tCSF0 | 0.85 | 1.05 | 1.27 | µs | RRDM < RRDM(TH) for VSET = 0 V | 14 |
| RRDM threshold for CS pin fault | RRDM(TH) | 35 | 55 | 70 | kΩ |  | 14 |
| Shut-down voltage of input OVP | VIOVPTH | 4.3 | 4.5 | 4.67 | V | FLT voltage increasing | 14 |
| NTC shut-down voltage | VNTCTH | 0.47 | 0.5 | 0.52 | V | FLT voltage decreasing | 14 |
| SWS zero voltage threshold (VSET = 0 V) | VTH(SWS) | 3.7 | 4.04 | 4.4 | V | VSET = 0 V | 14 |
| SWS zero voltage threshold (VSET = 5 V) | VTH(SWS) | 8.1 | 8.5 | 9.1 | V | VSET = 5 V | 14 |
| Maximum programmable dead time from PWMH low to PWML high | tZ(MAX) | 397.8 | 478 | 592.8 | ns | RRTZ = 280 kΩ, IVSL = -1 mA, VSET = 5 V | 14 |
| Maximum PWMH width with maximum tuning (UCC28782AD, UCC28782BDL, UCC28782CD) | tDM(MAX) | 6 | 6.95 | 7.53 | µs | VSWS = 12 V | 15 |
| Minimum PWMH width with minimum tuning (UCC28782AD, UCC28782BDL, UCC28782CD) | tDM(MIN) | 3 | 3.43 | 3.77 | µs | VSWS = 0 V | 15 |
| Clamping voltage for XCD OVP | VXCD(OVP) | 23 | 26 | 30 | V | IXCD = 20 mA | 15 |
| Maximum XCD discharge current | IXCD(MAX) | 1.65 | 2 | 2.5 | mA | VXCD = 15 V | 15 |
| Dwell time for each XCD sense step (UCC28782AD, UCC28782BDL, UCC28782CD) | tXCD(STEP) | 9 | 12 | 14 | ms |  | 15 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper |  | to minimize the regulator output switching loop area. Rather than with the BGND pin, the low-noise ground terminal of CVDD should be used to connect the BGND net to the AGND pin with a low im | 36 |

## CAD (KiCad official)

- Symbol: `UCC28782ADRTWR`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm`
- 3D model: WQFN-24(4x4) (KiCad packages3D, STEP)
- 3D model files: `ucc28782adrtwr-etched.step` / `ucc28782adrtwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ucc28782adrtwr.step` / `ucc28782adrtwr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ucc28782) (100 pp, sha256 `8ad1796404544817`, retrieved 2026-10-21, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ucc28782adrtwr-datasheet.pdf)