component
UCC28610DR
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownUCC28610DR
Texas Instruments · AC-DC Controllers And Regulators · SOIC-8
UCC28610DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Feedback current input that commands operating mode; FB voltage is clamped at 0.7 V and pin only detects current. |
| 2 | ZCD | input | Zero current detection input that senses transformer reset and programs output overvoltage protection using a resistive divider on the primary bias winding. |
| 3 | CL | input | Current limit programming input that sets peak primary inductor current through resistor to GND; RCL range 24.3 kΩ to 100 kΩ. |
| 4 | MOT | input | Maximum on-time programming input; sets tMOT of internal driver, programs overcurrent and under-voltage response mode (shutdown/retry or latch-off), and enables external shutdown when pulled to GND. |
| 5 | VGG | power_in | Gate drive supply voltage input (9-13 V from low-impedance source); requires 0.1-μF ceramic bypass capacitor to GND placed as close as possible and receives start-up bias through large-value resistor from input bulk voltage. |
| 6 | DRV | output | Gate drive output that drives the source of external high-voltage MOSFET; carries full primary current and requires Schottky diode between DRV and VDD for initial start-up bias. |
| 7 | GND | power_in | Ground and current return terminal for analog and power signals; carries full primary current; bulk capacitor return path must be separated from return paths of FB, ZCD, MOT, and CL. |
| 8 | VDD | power_in | Bias supply voltage input (9-20 V recommended operating range) derived from external source or auxiliary winding; requires 0.1-μF ceramic bypass capacitor placed between VDD and GND as close to device as possible. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
UCC28610DR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ucc28610dr-etched.step/ucc28610dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucc28610dr.step/ucc28610dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (51 pp, sha256
def444690b497c7d, retrieved 2026-10-01, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).