UCC28513DWR

Texas Instruments · AC-DC Controllers And Regulators · SOIC-20-300mil

UCC28513DWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VAOUT	bidirectional	Output of the PFC transconductance voltage amplifier, operating between GND and 5.5 V maximum, with the zero power detect comparator turning off the PFC gate drive when it falls below 0.33 V.
2	RT	input	A resistor between RT and GND programs the oscillator frequency measured at CT_BUFF, with a recommended range of 45 kΩ to 500 kΩ for 600 kHz to 65 kHz, and the pin is nominally 3 V DC and should not have a capacitor added.
3	VSENSE	input	Inverting input to the PFC transconductance voltage amplifier, which also feeds the OVP, ENABLE and UVLO2 comparators.
4	D_MAX	input	Positive input that sets the PWM maximum duty cycle, linearly related between 0.09 and 0.90, and setting it below 0.7 V sets DMAX to 0.
5	CT_BUFF	output	Internally buffered 4-V-amplitude PWM oscillator ramp output that can drive a typical 500-µA resistive load for slope compensation.
6	GND	power_in	Analog signal ground to which all voltages are referenced, with PWRGND required to be externally connected to this pin and VCC and VREF bypass capacitors returned here.
7	VERR	input	Feedback error voltage input for the PWM stage, clamped to a maximum of 3 V, able to demand 100% duty cycle at GT2, with a typical 10 µA pull-up current.
8	ISENSE2	input	Input for PWM stage current sense and peak current limit, with the peak limit threshold set to 1.3 V for peak current mode control.
9	VCC	power_in	Positive chip supply that should be held between 12 V and 17 V for normal operation with at least 20 mA available, bypassed directly to GND with a 0.1 µF or larger ceramic capacitor.
10	GT2	output	PWM stage gate drive output, a totem-pole MOSFET driver with 2-A peak source and 3-A peak sink current.
11	PWRGND	power_in	Ground for the GT1 and GT2 output drivers, which should be tied to GND externally via a single Kelvin connection.
12	GT1	output	PFC stage gate drive output, a totem-pole MOSFET driver with 2-A peak source and 3-A peak sink current, disabled unless VCC is outside the UVLO region and VREF is on.
13	SS2	input	Soft-start capacitor pin for the PWM stage, charged by an internal 10.5-µA source to 3 V and quickly discharged to ground on a disable command or UVLO2 dropout.
14	PKLMT	input	Voltage input to the PFC peak current limit comparator, with the threshold at 0 V, shifted from the PFC sense resistor voltage by a divider from VREF.
15	CAOUT	output	Output of the PFC current sense amplifier, internally connected to the PFC PWM comparator input, which can swing close to GND for maximum duty cycle and above the PFC ramp peak for zero duty cycle.
16	ISENSE1	input	Non-inverting input to the PFC current amplifier, connected through a resistor to the grounded side of the PFC current sense resistor.
17	MOUT	bidirectional	High-impedance PFC multiplier current output internally connected to the current amplifier inverting input, with the PFC power range set by a resistor to the non-grounded end of the sense resistor.
18	IAC	input	Multiplier current input that senses the rectified AC line voltage, with a recommended maximum IAC current of 500 µA.
19	VFF	input	Voltage feedforward pin that sources an IAC/2 current to an external single-pole R/C filter to GND, with VFF set to 1.4 V at low line.
20	VREF	power_out	Precision 7.5-V reference output that can deliver over 10 mA, is current limited to 25 mA, and should be bypassed with a 0.1 µF to 10 µF ceramic capacitor.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-20-300mil
Category	Power Management (PMIC)
Pins	20

CAD (KiCad official)

Symbol: UCC28513DWR
Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
3D model: SOIC-20-300mil (KiCad packages3D, STEP)
3D model files: ucc28513dwr-etched.step / ucc28513dwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc28513dwr.step / ucc28513dwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (42 pp, sha256 3a9542f6a46c942b, retrieved 2026-10-11, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# UCC28513DWR

**Texas Instruments** · AC-DC Controllers And Regulators · SOIC-20-300mil

UCC28513DWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VAOUT | bidirectional | Output of the PFC transconductance voltage amplifier, operating between GND and 5.5 V maximum, with the zero power detect comparator turning off the PFC gate drive when it falls below 0.33 V. |
| 2 | RT | input | A resistor between RT and GND programs the oscillator frequency measured at CT_BUFF, with a recommended range of 45 kΩ to 500 kΩ for 600 kHz to 65 kHz, and the pin is nominally 3 V DC and should not have a capacitor added. |
| 3 | VSENSE | input | Inverting input to the PFC transconductance voltage amplifier, which also feeds the OVP, ENABLE and UVLO2 comparators. |
| 4 | D_MAX | input | Positive input that sets the PWM maximum duty cycle, linearly related between 0.09 and 0.90, and setting it below 0.7 V sets DMAX to 0. |
| 5 | CT_BUFF | output | Internally buffered 4-V-amplitude PWM oscillator ramp output that can drive a typical 500-µA resistive load for slope compensation. |
| 6 | GND | power_in | Analog signal ground to which all voltages are referenced, with PWRGND required to be externally connected to this pin and VCC and VREF bypass capacitors returned here. |
| 7 | VERR | input | Feedback error voltage input for the PWM stage, clamped to a maximum of 3 V, able to demand 100% duty cycle at GT2, with a typical 10 µA pull-up current. |
| 8 | ISENSE2 | input | Input for PWM stage current sense and peak current limit, with the peak limit threshold set to 1.3 V for peak current mode control. |
| 9 | VCC | power_in | Positive chip supply that should be held between 12 V and 17 V for normal operation with at least 20 mA available, bypassed directly to GND with a 0.1 µF or larger ceramic capacitor. |
| 10 | GT2 | output | PWM stage gate drive output, a totem-pole MOSFET driver with 2-A peak source and 3-A peak sink current. |
| 11 | PWRGND | power_in | Ground for the GT1 and GT2 output drivers, which should be tied to GND externally via a single Kelvin connection. |
| 12 | GT1 | output | PFC stage gate drive output, a totem-pole MOSFET driver with 2-A peak source and 3-A peak sink current, disabled unless VCC is outside the UVLO region and VREF is on. |
| 13 | SS2 | input | Soft-start capacitor pin for the PWM stage, charged by an internal 10.5-µA source to 3 V and quickly discharged to ground on a disable command or UVLO2 dropout. |
| 14 | PKLMT | input | Voltage input to the PFC peak current limit comparator, with the threshold at 0 V, shifted from the PFC sense resistor voltage by a divider from VREF. |
| 15 | CAOUT | output | Output of the PFC current sense amplifier, internally connected to the PFC PWM comparator input, which can swing close to GND for maximum duty cycle and above the PFC ramp peak for zero duty cycle. |
| 16 | ISENSE1 | input | Non-inverting input to the PFC current amplifier, connected through a resistor to the grounded side of the PFC current sense resistor. |
| 17 | MOUT | bidirectional | High-impedance PFC multiplier current output internally connected to the current amplifier inverting input, with the PFC power range set by a resistor to the non-grounded end of the sense resistor. |
| 18 | IAC | input | Multiplier current input that senses the rectified AC line voltage, with a recommended maximum IAC current of 500 µA. |
| 19 | VFF | input | Voltage feedforward pin that sources an IAC/2 current to an external single-pole R/C filter to GND, with VFF set to 1.4 V at low line. |
| 20 | VREF | power_out | Precision 7.5-V reference output that can deliver over 10 mA, is current limited to 25 mA, and should be bypassed with a 0.1 µF to 10 µF ceramic capacitor. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20-300mil |
| Category | Power Management (PMIC) |
| Pins | 20 |

## CAD (KiCad official)

- Symbol: `UCC28513DWR`
- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`
- 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files: `ucc28513dwr-etched.step` / `ucc28513dwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ucc28513dwr.step` / `ucc28513dwr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ucc28512) (42 pp, sha256 `3a9542f6a46c942b`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ucc28513dwr-datasheet.pdf)