component
UCC28512DWR
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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UCC28512DWR
Texas Instruments · AC-DC Controllers And Regulators · SOIC-20-300mil
UCC28512DWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VAOUT | bidirectional | Output of the PFC transconductance voltage amplifier, operating between GND and 5.5 V maximum; when it falls below 0.33 V the zero power detect comparator turns off the PFC gate drive. |
| 2 | RT | input | Oscillator programming pin; a resistor from RT to GND sets the oscillator frequency measured at CT_BUFF, with a recommended range of 45 kΩ to 500 kΩ for 600 kHz to 65 kHz. |
| 3 | VSENSE | input | Inverting input to the PFC transconductance voltage amplifier, also connected to the OVP, ENABLE and UVLO2 comparators. |
| 4 | D_MAX | input | Positive input that sets the PWM stage maximum duty cycle; duty ratio is linear with D_MAX between 0.09 and 0.90, and a voltage below 0.7 V sets DMAX to 0. |
| 5 | CT_BUFF | output | Internally buffered 4-V PWM oscillator ramp output used for slope compensation through a resistor to ISENSE2, able to drive a typical 500 µA resistive load. |
| 6 | GND | power_in | Signal ground for the IC; all measured voltages are referenced to this pin, VCC and VREF bypass capacitors return here, and PWRGND must be externally connected to it. |
| 7 | VERR | input | Feedback error voltage input for the PWM stage that controls the GT2 duty cycle; it is clamped to a maximum of 3 V and can demand 100% duty cycle. |
| 8 | ISENSE2 | input | Input for PWM stage current sense and peak current limit, with the peak limit threshold set to 1.3 V for peak current mode control. |
| 9 | VCC | power_in | Positive supply pin that should be connected to a stable source of at least 20 mA between 12 V and 17 V for normal operation, bypassed to GND with a 0.1 µF or larger ceramic capacitor. |
| 10 | GT2 | output | PWM stage gate drive output, a 2-A peak source and 3-A peak sink totem-pole MOSFET driver. |
| 11 | PWRGND | power_in | Ground for the GT1 and GT2 output drivers, which must be tied to GND externally via a single Kelvin connection. |
| 12 | GT1 | output | PFC stage gate drive output, a 2-A peak source and 3-A peak sink totem-pole MOSFET driver that is disabled unless VCC is outside UVLO and VREF is on. |
| 13 | SS2 | input | Soft-start pin for the PWM stage; a capacitor to GND sets the soft-start time using a 10.5 µA charge current to 3 V, and SS2 quickly discharges on disable or UVLO2 dropout. |
| 14 | PKLMT | input | Voltage input to the PFC peak current limit comparator, with a threshold of 0 V, typically level-shifted from VREF through a resistor divider. |
| 15 | CAOUT | output | Output of the PFC wide-bandwidth current amplifier that commands the PFC PWM comparator duty cycle, with current loop compensation connected between CAOUT and MOUT. |
| 16 | ISENSE1 | input | Non-inverting input of the PFC stage current amplifier, connected through a resistor to the grounded side of the PFC current sense resistor. |
| 17 | MOUT | bidirectional | High-impedance PFC multiplier current output internally tied to the current amplifier inverting input; a resistor to the ungrounded end of the PFC sense resistor sets the PFC power range. |
| 18 | IAC | input | Multiplier current input proportional to the instantaneous rectified line voltage, with a recommended maximum IAC current of 500 µA. |
| 19 | VFF | input | Voltage feedforward pin that sources an IAC/2 current, which must be externally filtered by a single-pole R/C to GND; at low line VFF should be set to 1.4 V. |
| 20 | VREF | power_out | Output of an accurate 7.5-V reference that powers internal circuitry and can deliver over 10 mA, current limited to 25 mA, bypassed with a 0.1 µF to 10 µF ceramic capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20-300mil |
| Category | Power Management (PMIC) |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
UCC28512DWR - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files:
ucc28512dwr-etched.step/ucc28512dwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucc28512dwr.step/ucc28512dwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (42 pp, sha256
3a9542f6a46c942b, retrieved 2026-10-12, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# UCC28512DWR
**Texas Instruments** · AC-DC Controllers And Regulators · SOIC-20-300mil
UCC28512DWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VAOUT | bidirectional | Output of the PFC transconductance voltage amplifier, operating between GND and 5.5 V maximum; when it falls below 0.33 V the zero power detect comparator turns off the PFC gate drive. |
| 2 | RT | input | Oscillator programming pin; a resistor from RT to GND sets the oscillator frequency measured at CT_BUFF, with a recommended range of 45 kΩ to 500 kΩ for 600 kHz to 65 kHz. |
| 3 | VSENSE | input | Inverting input to the PFC transconductance voltage amplifier, also connected to the OVP, ENABLE and UVLO2 comparators. |
| 4 | D_MAX | input | Positive input that sets the PWM stage maximum duty cycle; duty ratio is linear with D_MAX between 0.09 and 0.90, and a voltage below 0.7 V sets DMAX to 0. |
| 5 | CT_BUFF | output | Internally buffered 4-V PWM oscillator ramp output used for slope compensation through a resistor to ISENSE2, able to drive a typical 500 µA resistive load. |
| 6 | GND | power_in | Signal ground for the IC; all measured voltages are referenced to this pin, VCC and VREF bypass capacitors return here, and PWRGND must be externally connected to it. |
| 7 | VERR | input | Feedback error voltage input for the PWM stage that controls the GT2 duty cycle; it is clamped to a maximum of 3 V and can demand 100% duty cycle. |
| 8 | ISENSE2 | input | Input for PWM stage current sense and peak current limit, with the peak limit threshold set to 1.3 V for peak current mode control. |
| 9 | VCC | power_in | Positive supply pin that should be connected to a stable source of at least 20 mA between 12 V and 17 V for normal operation, bypassed to GND with a 0.1 µF or larger ceramic capacitor. |
| 10 | GT2 | output | PWM stage gate drive output, a 2-A peak source and 3-A peak sink totem-pole MOSFET driver. |
| 11 | PWRGND | power_in | Ground for the GT1 and GT2 output drivers, which must be tied to GND externally via a single Kelvin connection. |
| 12 | GT1 | output | PFC stage gate drive output, a 2-A peak source and 3-A peak sink totem-pole MOSFET driver that is disabled unless VCC is outside UVLO and VREF is on. |
| 13 | SS2 | input | Soft-start pin for the PWM stage; a capacitor to GND sets the soft-start time using a 10.5 µA charge current to 3 V, and SS2 quickly discharges on disable or UVLO2 dropout. |
| 14 | PKLMT | input | Voltage input to the PFC peak current limit comparator, with a threshold of 0 V, typically level-shifted from VREF through a resistor divider. |
| 15 | CAOUT | output | Output of the PFC wide-bandwidth current amplifier that commands the PFC PWM comparator duty cycle, with current loop compensation connected between CAOUT and MOUT. |
| 16 | ISENSE1 | input | Non-inverting input of the PFC stage current amplifier, connected through a resistor to the grounded side of the PFC current sense resistor. |
| 17 | MOUT | bidirectional | High-impedance PFC multiplier current output internally tied to the current amplifier inverting input; a resistor to the ungrounded end of the PFC sense resistor sets the PFC power range. |
| 18 | IAC | input | Multiplier current input proportional to the instantaneous rectified line voltage, with a recommended maximum IAC current of 500 µA. |
| 19 | VFF | input | Voltage feedforward pin that sources an IAC/2 current, which must be externally filtered by a single-pole R/C to GND; at low line VFF should be set to 1.4 V. |
| 20 | VREF | power_out | Output of an accurate 7.5-V reference that powers internal circuitry and can deliver over 10 mA, current limited to 25 mA, bypassed with a 0.1 µF to 10 µF ceramic capacitor. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20-300mil |
| Category | Power Management (PMIC) |
| Pins | 20 |
## CAD (KiCad official)
- Symbol: `UCC28512DWR`
- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`
- 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files: `ucc28512dwr-etched.step` / `ucc28512dwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ucc28512dwr.step` / `ucc28512dwr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ucc28512) (42 pp, sha256 `3a9542f6a46c942b`, retrieved 2026-10-12, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ucc28512dwr-datasheet.pdf)