component
UCC28500DW
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownUCC28500DW
Texas Instruments · AC-DC Controllers And Regulators · SOIC-20-300mil
UCC28500DW from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VAOUT | output | Voltage amplifier output that regulates the output voltage and is internally limited to approximately 5.5 V to prevent overshoot. |
| 2 | RT | passive | Oscillator charging-current programming pin; a resistor from RT to GND sets the charging current, with 10 kΩ to 100 kΩ recommended and a nominal pin voltage of 3 V. |
| 3 | VSENSE | input | Inverting input of the voltage amplifier, normally connected to the compensation network and to the boost output through a divider network. |
| 4 | OVP/ENBL | input | Window-comparator input that disables the PFC driver if the boost output is 6.67% above nominal, disables both drivers and resets SS2 if pulled below 1.9 V, and sets the active range of the second-stage PWM. |
| 5 | CT | passive | Oscillator timing capacitor pin; a capacitor from CT to GND, with RT, sets the oscillator frequency, and its return lead should be as short as possible. |
| 6 | GND | power_in | Ground reference for all voltages; VCC and VREF should be bypassed directly to GND with a 0.1 µF or larger ceramic capacitor. |
| 7 | VERR | input | Error-signal input for the second stage, driven by an external amplifier, with an internal 4.5 V clamp that limits GT2 to less than 50% duty cycle. |
| 8 | ISENSE2 | input | Second-stage current-sense input, fed by a resistor from the lower FET source to ground, which may also sum the oscillator ramp for slope compensation. |
| 9 | VCC | power_in | Positive supply, to be connected to at least 20 mA between 12 V and 17 V for normal operation, bypassed directly to GND, and with outputs inhibited unless VCC exceeds the upper UVLO threshold. |
| 10 | GT2 | output | Totem-pole MOSFET gate-drive output for the second stage, limited to a 50% maximum duty cycle. |
| 11 | PWRGND | power_in | Ground return for the totem-pole output drivers. |
| 12 | GT1 | output | Totem-pole MOSFET gate-drive output for the PFC stage, which requires a series gate resistor of at least 10.5 Ω to limit overshoot. |
| 13 | SS2 | passive | Soft-start pin for the second-stage PWM, charged by an external capacitor through a current source and quickly discharged on a disable command or UVLO2 dropout. |
| 14 | PKLMT | input | PFC peak current-limit input with a 0 V threshold, where a level-shift divider from the current-sense resistor to VREF sets the overcurrent level. |
| 15 | CAOUT | output | Output of the wide-bandwidth current amplifier that commands the PFC PWM duty cycle and can swing close to GND to allow zero duty cycle. |
| 16 | ISENSE1 | input | Non-inverting input of the current amplifier, which remains functional down to and below GND. |
| 17 | MOUT | input | Multiplier output and inverting input of the current amplifier, a high-impedance node to which current-loop compensation connects between MOUT and CAOUT. |
| 18 | IAC | input | Analog multiplier current input used to sense instantaneous line voltage, with a recommended maximum of 500 µA. |
| 19 | VFF | output | RMS feed-forward signal generated by mirroring one-half of IAC into a single-pole external filter, which should be 1.4 V at low line. |
| 20 | VREF | power_out | Accurate 7.5 V reference output capable of supplying 10 mA to peripheral circuitry, internally short-circuit current limited, and bypassed to GND with 0.1 µF or larger ceramic. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20-300mil |
| Category | Power Management (PMIC) |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
UCC28500DW - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files:
ucc28500dw-etched.step/ucc28500dw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucc28500dw.step/ucc28500dw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (36 pp, sha256
5eaadcc6a0fa5e00, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).