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UCC2810DW

Texas Instruments · AC-DC Controllers And Regulators · SOIC-16-300mil

UCC2810DW from Texas Instruments, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SYNC input Edge-triggered TTL-threshold logic input that synchronizes the oscillator to an external free-running oscillator, requiring a pulse at least 10 ns wide; if unused it may be grounded, left open, or connected to REF.
2 CT passive Oscillator timing capacitor node; recommended CT is between 100 pF and 1 nF, connected directly across CT and GND.
3 RT passive Oscillator timing resistor node, regulated to 1 V, with recommended values between 10 kΩ and 470 kΩ; higher RT gives higher maximum duty cycle and slightly lower power consumption.
4 FB1 input High-impedance inverting input of error amplifier 1.
5 COMP1 output Low-impedance output of error amplifier 1.
6 CS1 input Current-sense input to PWM comparator 1 with leading-edge blanking that ignores the signal for the first 55 ns of each PWM cycle; a small R-C filter may be needed in noisy or slow-diode applications.
7 OUT1 output High-current push-pull output for PWM 1 intended to drive a power MOSFET gate through a small series resistor.
8 GND power_in Control-circuit ground that must be electrically connected to PWRGND while keeping noise out of this pin.
9 PWRGND power_in Power ground for the output stages that must be electrically connected to GND.
10 OUT2 output High-current push-pull output for PWM 2 intended to drive a power MOSFET gate through a small series resistor.
11 CS2 input Current-sense input to PWM comparator 2 with leading-edge blanking for the first 55 ns of each PWM cycle; a small R-C filter may be needed in noisy or slow-diode applications.
12 COMP2 output Low-impedance output of error amplifier 2.
13 FB2 input High-impedance inverting input of error amplifier 2.
14 ENABLE2 input TTL-compatible logic input that disables PWM 2 when low, has no effect on PWM 1, and is internally pulled high (may be left floating).
15 REF power_out 5-V reference output that should be bypassed to GND with a ceramic capacitor of at least 0.01 µF.
16 VCC power_in Power input supplying all device functions including the high-current output stages and precision reference, to be bypassed directly to PWRGND with a 0.1 µF ceramic capacitor.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16-300mil
Category Power Management (PMIC)
Pins 16

CAD (KiCad official)

  • Symbol: UCC2810DW
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: ucc2810dw-etched.step / ucc2810dw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc2810dw.step / ucc2810dw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 b7a04f61c8240c01, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF