component
UCC2809DTR-2
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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UCC2809DTR-2
Texas Instruments · AC-DC Controllers And Regulators · SOIC-8
UCC2809DTR-2 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Summing node for current-sense feedback, optocoupler voltage feedback and slope compensation, compared against a 1 V threshold; an internal 250 Ω NMOS discharges external leading-edge-blanking capacitance during the PWM off time. |
| 2 | SS | passive | Soft-start timing capacitor node charged by an internal 6 µA source; the output driver is held low while SS is below 0.5 V (shutdown threshold 0.44-0.52 V), and the duty cycle ramps as SS charges from 1 V to 2 V. |
| 3 | RT1 | passive | Timing resistor RT1 connection that sets the positive ramp time of the oscillator, Tr = 0.74 × (CT + 27 pF) × RT1, with a recommended minimum of 10 kΩ. |
| 4 | RT2 | passive | Timing resistor RT2 connection that sets the negative ramp time of the oscillator, Tf = 0.74 × (CT + 27 pF) × RT2, with a recommended minimum of 4.32 kΩ. |
| 5 | GND | power_in | Reference ground and power ground for all functions of the device. |
| 6 | OUT | output | High-current totem-pole gate driver output for an N-channel MOSFET, rated -0.4 A to 0.8 A (tpw < 1 µs, duty cycle < 10%), with a minimum series gate resistor of 3.9 Ω recommended at high bias voltages. |
| 7 | VDD | power_in | Supply input shunt-regulated at 17.5 V (VDD clamp 16-19 V at 10 mA), with an absolute maximum rating of 19 V, to be bypassed with a 1 µF ceramic capacitor. |
| 8 | REF | power_out | Internal buffered 5 V reference output (4.75-5.25 V at IREF = 0 mA, IREF limited to -15 mA absolute maximum), to be bypassed with at least 0.47 µF ceramic capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
UCC2809DTR-2 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ucc2809dtr-2-etched.step/ucc2809dtr-2-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucc2809dtr-2.step/ucc2809dtr-2.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (24 pp, sha256
7fc852aa75a77966, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# UCC2809DTR-2
**Texas Instruments** · AC-DC Controllers And Regulators · SOIC-8
UCC2809DTR-2 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Summing node for current-sense feedback, optocoupler voltage feedback and slope compensation, compared against a 1 V threshold; an internal 250 Ω NMOS discharges external leading-edge-blanking capacitance during the PWM off time. |
| 2 | SS | passive | Soft-start timing capacitor node charged by an internal 6 µA source; the output driver is held low while SS is below 0.5 V (shutdown threshold 0.44-0.52 V), and the duty cycle ramps as SS charges from 1 V to 2 V. |
| 3 | RT1 | passive | Timing resistor RT1 connection that sets the positive ramp time of the oscillator, Tr = 0.74 × (CT + 27 pF) × RT1, with a recommended minimum of 10 kΩ. |
| 4 | RT2 | passive | Timing resistor RT2 connection that sets the negative ramp time of the oscillator, Tf = 0.74 × (CT + 27 pF) × RT2, with a recommended minimum of 4.32 kΩ. |
| 5 | GND | power_in | Reference ground and power ground for all functions of the device. |
| 6 | OUT | output | High-current totem-pole gate driver output for an N-channel MOSFET, rated -0.4 A to 0.8 A (tpw < 1 µs, duty cycle < 10%), with a minimum series gate resistor of 3.9 Ω recommended at high bias voltages. |
| 7 | VDD | power_in | Supply input shunt-regulated at 17.5 V (VDD clamp 16-19 V at 10 mA), with an absolute maximum rating of 19 V, to be bypassed with a 1 µF ceramic capacitor. |
| 8 | REF | power_out | Internal buffered 5 V reference output (4.75-5.25 V at IREF = 0 mA, IREF limited to -15 mA absolute maximum), to be bypassed with at least 0.47 µF ceramic capacitor. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `UCC2809DTR-2`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ucc2809dtr-2-etched.step` / `ucc2809dtr-2-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ucc2809dtr-2.step` / `ucc2809dtr-2.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ucc2809-2) (24 pp, sha256 `7fc852aa75a77966`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ucc2809dtr-2-datasheet.pdf)