component
UCC28086D
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 29d ago |
| viewers | 29d ago |
| package.json | 29d ago |
| page.json | 25d ago |
| README.md | 25d ago |
| ucc28086d-etched.glb | 29d ago |
| ucc28086d-etched.step | 29d ago |
| ucc28086d-hero.glb | 29d ago |
| ucc28086d-hero.overlay.json | 29d ago |
| ucc28086d.glb | 29d ago |
| ucc28086d.kicad_mod | 29d ago |
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| ucc28086d.lbr | 29d ago |
| ucc28086d.step | 29d ago |
UCC28086D
Texas Instruments · DC-DC Converters · SOIC-8
UCC28086D from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CTRL | input | Error voltage input to the PWM comparator, with an internal divider ratio of 0.45 to keep a usable range at the minimum VDD of 4.1 V; absolute maximum is -0.3 V to VDD + 0.3 V. |
| 2 | ISET | input | Slope-compensation current selection pin, where a resistor RSET from ISET to ground programs the ramp with ISLOPE = 5 × ISET; RSET must be greater than 5 kΩ per the absolute maximum ratings. |
| 3 | CS | input | Current-sense input to the PWM comparator, cycle-by-cycle peak current comparator and overcurrent comparator, where exceeding the overcurrent threshold (0.70 V to 0.80 V) causes a soft-start cycle; absolute maximum is -0.3 V to VDD + 0.3 V, not to exceed 6 V. |
| 4 | RT | input | Oscillator programming pin, where a timing resistor from RT to GND sets the oscillator frequency over a recommended range of 25 kΩ to 698 kΩ, with a nominal RT voltage of 1.5 V (1.2 V to 1.6 V) and an absolute maximum range of -0.3 V to 2.0 V. |
| 5 | GND | power_in | Reference ground and power ground for all functions, where a low-impedance circuit board ground plane is highly recommended because of high currents and high-frequency operation. |
| 6 | OUTB | output | High-current push-pull output stage, alternating with OUTA at half the oscillator frequency, capable of 500 mA peak source and 1 A peak sink to drive a power MOSFET gate. |
| 7 | OUTA | output | High-current push-pull output stage, alternating with OUTB at half the oscillator frequency, capable of 500 mA peak source and 1 A peak sink to drive a power MOSFET gate. |
| 8 | VDD | power_in | Power input connection, where a 1-µF ceramic decoupling capacitor close to the chip is recommended and the absolute maximum supply voltage is 15 V with IDD below 10 mA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Start-up current | 120 | 200 | µA | VDD < UVLO start threshold voltage | 3 | ||
| Supply current | 1.5 | 2.5 | mA | CTRL = 0 V, CS = 0 V, See Note 1 | 3 | ||
| Start threshold voltage UCC38084/6 | 4.1 | 4.3 | 4.5 | V | 3 | ||
| Minimum operating voltage after start UCC38084/6 | 3.9 | 4.1 | 4.3 | V | 3 | ||
| Hysteresis voltage UCC38084/6 | 0.1 | 0.2 | 0.3 | V | 3 | ||
| Oscillator frequency | 2 x f(OUTA) | 180 | 200 | 220 | kHz | 3 | |
| Oscillator voltage amplitude | 1.4 | 1.5 | 1.6 | V | See Note 2 | 3 | |
| Oscillator fall time (dead time) | 110 | 220 | ns | 3 | |||
| RT pin voltage | 1.2 | 1.5 | 1.6 | V | 3 | ||
| Gain | 1.9 | 2.2 | 2.5 | V/V | See Note 3 | 4 | |
| Maximum input signal voltage | 0.47 | 0.52 | 0.57 | V | CTRL = 5 V, See Note 4 | 4 | |
| CS to output delay time | 100 | 200 | ns | CTRL = 3.5 V, 0 mV ≤ CS ≤ 600 mV | 4 | ||
| Source current | -200 | nA | 4 | ||||
| Sink current | 3 | 7 | 12 | mA | CS = 0.5 V, RT = 2.0 V, See Note 5 | 4 | |
| Overcurrent threshold voltage | 0.7 | 0.75 | 0.8 | V | 4 | ||
| CTRL to CS offset voltage | 0.55 | 0.7 | 0.9 | V | CS = 0 V, 25°C | 4 | |
| CTRL to CS offset voltage | 0.37 | 0.7 | 1.1 | V | CS = 0 V | 4 | |
| Maximum duty cycle | 48 | 49 | 50 | % | Measured at OUTA or OUTB, See Note 7 | 4 | |
| Minimum duty cycle | 0 | % | CTRL = 0 V | 4 | |||
| Low-level output voltage (OUTA or OUTB) | 0.5 | 1 | V | IOUT = 100 mA | 4 | ||
| High-level output voltage (OUTA or OUTB) | 0.5 | 1 | V | IOUT = −50 mA, (VDD − VOUT), See Note 6 | 4 | ||
| Rise time | 25 | 60 | ns | CLOAD = 1 nF | 4 | ||
| Fall time | 25 | 60 | ns | CLOAD = 1 nF | 4 | ||
| OUTA/OUTB soft-start interval time, UCC38085/6 | 30 | 75 | 110 | µs | CTRL = 1.8 V, CS = 0 V, Duty cycle from 0 to full, See Note 8 | 4 | |
| Slope compensation ramp current (IRAMP, peak) | IRAMP | 125 | 150 | 175 | µA | ISET peak = 30 µA, Full duty cycle | 4 |
| Supply voltage VDD | VDD | 15 | V | IDD < 10 mA | 3 | ||
| Supply current IDD | IDD | 20 | mA | 3 | |||
| Sink current (peak): OUTA | 1 | A | 3 | ||||
| Sink current (peak): OUTB | 1 | A | 3 | ||||
| Source current (peak): OUTA | -0.5 | A | 3 | ||||
| Source current (peak): OUTB | -0.5 | A | 3 | ||||
| Analog input CTRL (upper limit VDD + 0.3 V) | -0.3 | V | 3 | ||||
| Analog input CS (upper limit VDD + 0.3 V, not to exceed 6 V) | -0.3 | V | 3 | ||||
| RSET (minimum) | RSET | 5 | kΩ | 3 | |||
| RT pin voltage (absolute maximum) | RT | -0.3 | 2 | V | −100 µA < IRT < 100 µA | 3 | |
| Power dissipation at TA = 25°C (P package) | 1 | W | TA = 25°C | 3 | |||
| Power dissipation at TA = 25°C (D package) | 650 | mW | TA = 25°C | 3 | |||
| Power dissipation at TA = 25°C (PW package) | 400 | mW | TA = 25°C | 3 | |||
| Junction operating temperature | TJ | -55 | 150 | °C | 3 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Lead temperature | 300 | °C | soldering 10 seconds | 3 | |||
| Thermal resistance junction to ambient, SOIC-8 (D) | θja | 84 | 160 | °C/W | devices mounted to 5-inch² FR4 PC board with one ounce copper | 2 | |
| Thermal resistance junction to case, SOIC-8 (D) | θjc | 42 | °C/W | 2 |
CAD (KiCad official)
- Symbol:
UCC28086D - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ucc28086d-etched.step/ucc28086d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucc28086d.step/ucc28086d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (28 pp, sha256
19bab60962d5c6f5, retrieved 2026-10-12, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).