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Contents

README

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UCC28063ADR

Texas Instruments · AC-DC Controllers And Regulators · SOIC-16

UCC28063ADR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ZCDB input Zero-current detection input for phase B with 1.0V falling threshold and 1.7V rising threshold; input clamped between 0V and 3V.
2 VSENSE input Output voltage sense input regulated to 6.0V reference with 1.25V enable threshold; overvoltage protection thresholds at 6.48V and 6.67V.
3 TSET input Timing set resistor input to ground (66.5kΩ to 400kΩ range) for programming PWM on-time factor and minimum switching period between 25kHz and 50kHz.
4 PHB input Phase B enable/disable control input; below 0.8V threshold disables phase B and phase-fail detection; above 1.0V threshold enables two-phase operation.
5 COMP output Error amplifier transconductance output for voltage-regulation loop compensation with 55µS small-signal gain and 5X large-signal gain; output range 0V to 4.95V.
6 AGND power_in Analog ground connection for signal bypass capacitors, compensation networks, and analog circuit returns; star-connected with PGND to minimize differential voltage.
7 VINAC input Input AC voltage sense from rectified mains voltage divider with brownout threshold at 1.39V and dropout threshold at 0.35V; input range 0V to 6V.
8 HVSEN input High voltage output sense for FailSafe overvoltage protection with 4.87V fault threshold and 4.67V clear threshold; triggers PWMCNTL output when above 2.5V.
9 PWMCNTL tri_state Open-drain PWM control output for downstream converter enable/disable; pulled low when HVSEN exceeds 2.5V with no FailSafe overvoltage or phase-fail condition.
10 CS input Current sense input for cycle-by-cycle overcurrent protection with -200mV threshold in dual-phase mode and -166mV in single-phase mode; 100ns blanking after gate transitions.
11 GDB output Gate drive output for phase B power MOSFET with 1A source and 1.8A sink capability; output voltage clamped at 13.5V nominal.
12 VCC power_in Bias supply voltage input from regulated 14V to 21V source with maximum 20mA input current; bypass with 0.1µF ceramic capacitor located close to pin.
13 PGND power_in Power stage ground connection for gate drive and power supply return; star-connected with AGND to minimize DC and high-frequency voltage differential.
14 GDA output Gate drive output for phase A power MOSFET with 1A source and 1.8A sink capability; output voltage clamped at 13.5V nominal.
15 VREF power_in Voltage reference output providing regulated 6.00V ±0.18V for device internal circuits and external biasing with ±2mA load current capability.
16 ZCDA input Zero-current detection input for phase A with 1.0V falling threshold and 1.7V rising threshold; input clamped between 0V and 3V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Power Management (PMIC)
Pins 16

CAD (KiCad official)

  • Symbol: UCC28063ADR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: ucc28063adr-etched.step / ucc28063adr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc28063adr.step / ucc28063adr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (46 pp, sha256 e28a2680b1f9ffa9, retrieved 2026-09-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF