# UCC28061QDRQ1

**Texas Instruments** · AC-DC Controllers & Regulators · SOIC-16

UCC28061QDRQ1 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ZCDB | input | Zero current detection input for phase B, clamped at 0 V and 3 V, expects a negative edge (falling threshold ~1 V, rising ~1.7 V) via a series resistor limiting clamp current to less than ±3 mA. |
| 2 | VSENSE | input | Output DC voltage sense input from a divider across the converter output with 6 V error amplifier reference; pulling it low disables the outputs, and open-loop protection pulls it low if disconnected. |
| 3 | TSET | input | PWM on-time programming input; a resistor to AGND sets on-time versus COMP voltage and the minimum period at the gate drive outputs. |
| 4 | PHB | input | Phase B enable input that turns channel B on/off (doubling channel A on-time when disabled); connect to COMP for automatic phase management or to VREF to disable it. |
| 5 | COMP | output | Transconductance error amplifier output (high-impedance current source) for loop compensation to AGND; on-time is proportional to COMP minus ~125 mV and COMP is pulled low during soft-start events. |
| 6 | AGND | power_in | Analog ground for signal bypass capacitors, compensation components and analog returns, connected to power ground at a single point. |
| 7 | VINAC | input | Input AC voltage sense from a divider across the rectified mains; below the brownout threshold longer than the filter time both drives are disabled (recommended input range 0 to 6 V). |
| 8 | HVSEN | input | High voltage output sense for redundant fail-safe overvoltage protection and power-good enable of a downstream converter; must never fall below 0.8 V during operation. |
| 9 | PWMCNTL | output | Open-drain PWM enable output that goes low when HVSEN is in the good region and ZCDA/ZCDB are switching correctly, otherwise high impedance. |
| 10 | CS | input | Current sense input that goes negative with input current; cycle-by-cycle overcurrent turns off both gate drives at about -200 mV and releases at about -15 mV. |
| 11 | GDB | output | Channel B gate drive output to the power FET gate, with an optional 5-10 Ω series resistor to reduce ringing. |
| 12 | VCC | power_in | Bias supply input of 14 V to 21 V, bypassed with 0.1 µF to PGND, and must deliver 6 mA dc plus gate charging current. |
| 13 | PGND | power_in | Power ground for the integrated circuit, connected to AGND through a separate short trace to isolate gate driver noise. |
| 14 | GDA | output | Channel A gate drive output to the power FET gate, with an optional 5-10 Ω series resistor to reduce ringing. |
| 15 | VREF | power_out | 6 V reference output bypassed with 0.1 µF to AGND that can bias circuits needing less than 2 mA total and turns off during VCC undervoltage and VSENSE disable. |
| 16 | ZCDA | input | Zero current detection input for phase A, clamped at 0 V and 3 V, expects a negative edge (falling threshold ~1 V, rising ~1.7 V) via a series resistor limiting clamp current to less than ±3 mA. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Power Supply Chip |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC input voltage | VCC | -0.5 |  | 21 | V | wrt GND | 3 |
| PWMCNTL input voltage | PWMCNTL | -0.5 |  | 20 | V |  | 3 |
| COMP, CS, PHB, HVSEN, VINAC, VSENSE input voltage |  | -0.5 |  | 7 | V |  | 3 |
| ZCDA, ZCDB input voltage |  | -0.5 |  | 4 | V |  | 3 |
| VCC continuous input current |  |  |  | 20 | mA |  | 3 |
| PWMCNTL input current |  |  |  | 10 | mA |  | 3 |
| ZCDA, ZCDB, VSENSE input current |  | -5 |  | 5 | mA |  | 3 |
| VREF output current |  | -10 |  |  | mA |  | 3 |
| Continuous gate current GDA, GDB |  | -25 |  | 25 | mA |  | 3 |
| Operating junction temperature | TJ | -40 |  | 125 | °C |  | 3 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 3 |
| Lead temperature | TSOL |  |  | 260 | °C | Soldering, 10s | 3 |
| ESD HBM |  |  |  | 2000 | V | AEC-Q100 Classification Level H2 | 3 |
| ESD CDM |  |  |  | 750 | V | AEC-Q100 Classification Level C3B | 3 |
| Junction-to-ambient thermal resistance | θJA |  | 91.6 |  | °C/W | D (16 pin) | 3 |
| Junction-to-case (top) thermal resistance | θJCtop |  | 52.1 |  | °C/W | D (16 pin) | 3 |
| Junction-to-board thermal resistance | θJB |  | 48.6 |  | °C/W | D (16 pin) | 3 |
| Junction-to-top characterization parameter | ψJT |  | 14.9 |  | °C/W | D (16 pin) | 3 |
| Junction-to-board characterization parameter | ψJB |  | 48.3 |  | °C/W | D (16 pin) | 3 |
| VCC input voltage from low-impedance source | VCC | 14 |  | 21 | V |  | 3 |
| VCC input current from high-impedance source |  | 8 |  | 18 | mA |  | 3 |
| VREF load current |  | 0 |  | -2 | mA |  | 3 |
| VINAC input voltage |  | 0 |  | 6 | V |  | 3 |
| ZCDA, ZCDB series resistor |  | 20 |  | 80 | kΩ |  | 3 |
| TSET resistor to program PWM on-time | RTSET | 66.5 |  | 400 | kΩ |  | 3 |
| HVSEN input voltage |  | 0.8 |  | 4.5 | V |  | 4 |
| PWMCNTL pull-up resistor to VREF |  | 1 |  | 10 | kΩ |  | 4 |
| VCC shunt voltage | VCC(shunt) | 22 | 24 | 26 | V | IVCC = 10 mA | 4 |
| VCC current, disabled | IVCC(stby) |  | 100 | 200 | µA | VSENSE = 0 V | 4 |
| VCC current, enabled | IVCC(on) |  | 5 | 8 | mA | VSENSE = 6 V | 4 |
| VCC turn-on threshold | VCC(on) | 11.5 | 12.6 | 13.5 | V |  | 4 |
| VCC turn-off threshold | VCC(off) | 9.5 | 10.35 | 11.5 | V |  | 4 |
| UVLO hysteresis |  | 1.85 | 2.25 | 2.65 | V |  | 4 |
| VREF output voltage, no load | VREF | 5.82 | 6 | 6.18 | V | IVREF = 0 mA | 4 |
| VREF change with load |  |  | 1 | 6 | mV | 0 mA ≤ IVREF ≤ -2 mA | 4 |
| VREF change with VCC |  |  | 1 | 10 | mV | 12 V ≤ VCC ≤ 20 V | 4 |
| VSENSE input regulation voltage |  | 5.85 | 6 | 6.15 | V | TA = +25°C | 4 |
| VSENSE input regulation voltage |  | 5.82 | 6 | 6.18 | V |  | 4 |
| VSENSE input bias current |  | 125 | 300 | 800 | nA | In regulation | 4 |
| COMP high voltage, clamped |  | 4.7 | 4.95 | 5.1 | V | VSENSE = 5.8 V | 4 |
| COMP low voltage, saturated |  |  | 0.03 | 0.125 | V | VSENSE = 6.2 V | 4 |
| VSENSE to COMP transconductance | gm | 75 | 96 | 110 | µS | COMP = 3 V, 5.94 V < VSENSE < 6.06 V | 4 |
| COMP source current, overdriven |  | -120 | -160 | -190 | µA | VSENSE = 5 V, COMP = 3 V | 4 |
| COMP sink current |  | 7 | 20 | 32 | µA | VSENSE = 6.2 V, COMP = 3 V | 4 |
| VSENSE threshold for COMP offset enable, down |  | 135 | 185 | 235 | mV | Voltage below VREF | 4 |
| VSENSE over-voltage threshold, rising | VOVP | 6.25 | 6.45 | 6.7 | V |  | 4 |
| VSENSE over-voltage hysteresis |  | 0.1 | 0.2 | 0.4 | V |  | 4 |
| VSENSE enable threshold, rising |  | 1.15 | 1.25 | 1.35 | V |  | 4 |
| VSENSE enable hysteresis |  | 0.02 | 0.05 | 0.2 | V |  | 4 |
| HVSEN threshold to PWMCNTL | VPWMCNTL | 2.35 | 2.5 | 2.65 | V | HVSEN rising | 4 |
| HVSEN input bias current, high |  | -0.5 |  | 0.5 | µA | HVSEN = 3 V | 4 |
| HVSEN input bias current, low |  | 28 | 36 | 41 | µA | HVSEN = 2 V | 4 |
| HVSEN rising threshold to over-voltage fault |  | 4.64 | 4.87 | 5.1 | V |  | 4 |
| HVSEN falling threshold to over-voltage fault |  | 4.45 | 4.67 | 4.8 | V |  | 4 |
| Phase Fail filter time to PWMCNTL high |  | 8 | 12 | 20 | ms | PHB = 5 V, ZCDA switching, ZCDB = 0.5 V | 4 |
| PWMCNTL leakage current high |  | -1 |  | 1 | µA | HVSEN = 2 V, PWMCNTL = 15 V | 4 |
| PWMCNTL output voltage low |  |  | 0.2 | 0.5 | V | HVSENS = 3 V, IPWMCNTL = 5 mA | 4 |
| GDA, GDB output voltage high |  | 11.5 | 13 | 15 | V | IGDA, IGDB = -100 mA | 5 |
| GDA, GDB output voltage high, clamped |  | 12 | 13.5 | 15 | V | VCC = 20 V, IGDA, IGDB = -5 mA | 5 |
| GDA, GDB output voltage high, low VCC |  | 10 | 10.5 | 11.5 | V | VCC = 12 V, IGDA, IGDB = -5 mA | 5 |
| GDA, GDB on-resistance high |  |  | 8 | 14 | Ω | IGDA, IGDB = -100 mA | 5 |
| GDA, GDB output voltage low |  |  | 0.15 | 0.3 | V | IGDA, IGDB = 100 mA | 5 |
| GDA, GDB on-resistance low |  |  | 2 | 3 | Ω | IGDA, IGDB = 100 mA | 5 |
| Gate drive rise time |  |  | 18 | 30 | ns | 1 V to 9 V, CLOAD = 1 nF | 5 |
| Gate drive fall time |  |  | 12 | 25 | ns | 9 V to 1 V, CLOAD = 1 nF | 5 |
| GDA, GDB output voltage UV |  |  | 1.6 | 2 | V | IGDA, IGDB = 2.5 mA | 5 |
| ZCDA, ZCDB voltage threshold, falling |  | 0.8 | 1 | 1.2 | V |  | 5 |
| ZCDA, ZCDB voltage threshold, rising |  | 1.5 | 1.68 | 1.88 | V |  | 5 |
| ZCDA, ZCDB clamp, high |  | 2.6 | 3 | 3.4 | V | IZCDA = +2 mA, IZCDB = +2 mA | 5 |
| ZCDA, ZCDB input bias current |  | -0.5 |  | 0.5 | µA | ZCDA = 1.4 V, ZCDB = 1.4 V | 5 |
| ZCDA, ZCDB clamp, low |  | -0.4 | -0.2 | 0 | V | IZCDA = -2 mA, IZCDB = -2 mA | 5 |
| ZCDA, ZCDB delay to GDA, GDB outputs |  |  | 45 | 100 | ns | Respective gate drive output rising 10% from zero crossing input falling to 1 V | 5 |
| CS input bias current |  | -150 | -250 |  | µA | At rising threshold | 5 |

## CAD (KiCad official)

- Symbol: `UCC28061QDRQ1`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `ucc28061qdrq1-etched.step` / `ucc28061qdrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ucc28061qdrq1.step` / `ucc28061qdrq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ucc28061-q1) (33 pp, sha256 `0916ffb443732489`, retrieved 2026-10-23, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ucc28061qdrq1-datasheet.pdf)