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ucc28061dr
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Texas Instruments AC-DC Controllers And Regulators, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# UCC28061DR++**Texas Instruments** · AC-DC Controllers And Regulators · SOIC-16++UCC28061DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | ZCDB | input | Zero current detection input for phase B with 0-3 V clamp range, 1.0 V falling threshold, and 1.68 V rising threshold for inductor current decay monitoring. |+| 2 | VSENSE | input | Output voltage sense input for error amplifier feedback with 6 V reference; pullable low by open-drain logic to disable gate drivers. |+| 3 | TSET | input | Timing resistor connection to AGND that programs on-time factor and minimum switching period proportionally. |+| 4 | PHB | input | Phase B management input; pull high or to VREF for two-phase operation or to ground for single-phase operation. |+| 5 | COMP | output | Error amplifier transconductance output with 96 µS typical gain providing on-time control proportional to (COMP voltage - 125 mV). |+| 6 | AGND | power_in | Analog ground connection for bypass capacitors, compensation networks, and low-level analog signal returns. |+| 7 | VINAC | input | Input AC mains voltage sense input with 1.39 V brownout threshold and 440 ms filter delay time. |+| 8 | HVSEN | input | High voltage output sense for redundant FailSafe OVP with 4.87 V rising threshold; must stay above 0.8 V during normal operation. |+| 9 | PWMCNTL | tri_state | Open-drain PWM enable output that pulls low when output voltage in valid range and both ZCD inputs switching correctly in two-phase mode. |+| 10 | CS | input | Current sense input for shunt resistor with -200 mV rising threshold and -15 mV falling threshold for cycle-by-cycle overcurrent protection. |+| 11 | GDB | output | Gate drive output for phase B power FET with 1 A source and 1.8 A sink capability and 13 V typical high output voltage. |+| 12 | VCC | power_in | Bias supply input requiring regulated 14-21 V with 6 mA minimum DC capability plus transient gate charge current. |+| 13 | PGND | power_in | Power ground for integrated circuit isolated from analog ground via separate dedicated trace. |+| 14 | GDA | output | Gate drive output for phase A power FET with 1 A source and 1.8 A sink capability and 13 V typical high output voltage. |+| 15 | VREF | power_out | Reference voltage output providing 6.0 V regulated supply with 2 mA maximum load current capability. |+| 16 | ZCDA | input | Zero current detection input for phase A with 0-3 V clamp range, 1.0 V falling threshold, and 1.68 V rising threshold for inductor current decay monitoring. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16 |+| Category | Power Management (PMIC) |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `UCC28061DR`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `ucc28061dr-etched.step` / `ucc28061dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ucc28061dr.step` / `ucc28061dr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/ucc28061.pdf) (36 pp, sha256 `680a4a083278a849`, retrieved 2026-09-22, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ucc28061dr-datasheet.pdf)
page.jsonadded+189@@ -0,0 +1,189 @@+{+ "slug": "ucc28061dr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments AC-DC Controllers And Regulators, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "ucc28061dr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ucc28061dr.kicad_sym",+ "ucc28061dr.kicad_mod",+ "ucc28061dr.glb",+ "ucc28061dr.step",+ "ucc28061dr.lbr",+ "docs/hero.png",+ "docs/ucc28061dr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "UCC28061DR",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Power Management (PMIC)",+ "subcategory": "AC-DC Controllers And Regulators",+ "datasheet": "https://www.ti.com/lit/ds/symlink/ucc28061.pdf",+ "parts": {+ "symbol": "ucc28061dr.kicad_sym",+ "footprint": "ucc28061dr.kicad_mod",+ "model_3d": "ucc28061dr-etched.glb",+ "model_3d_plain": "ucc28061dr.glb",+ "model_3d_step": "ucc28061dr-etched.step",+ "model_3d_step_plain": "ucc28061dr.step",+ "lbr": "ucc28061dr.lbr"+ },+ "distributor_links": {+ "lcsc": "C523749"+ },+ "pins": [+ {+ "number": "1",+ "name": "ZCDB",+ "type": "input",+ "description": "Zero current detection input for phase B with 0-3 V clamp range, 1.0 V falling threshold, and 1.68 V rising threshold for inductor current decay monitoring."+ },+ {+ "number": "2",+ "name": "VSENSE",+ "type": "input",+ "description": "Output voltage sense input for error amplifier feedback with 6 V reference; pullable low by open-drain logic to disable gate drivers."+ },+ {+ "number": "3",+ "name": "TSET",+ "type": "input",+ "description": "Timing resistor connection to AGND that programs on-time factor and minimum switching period proportionally."+ },+ {+ "number": "4",+ "name": "PHB",+ "type": "input",+ "description": "Phase B management input; pull high or to VREF for two-phase operation or to ground for single-phase operation."+ },+ {+ "number": "5",+ "name": "COMP",+ "type": "output",+ "description": "Error amplifier transconductance output with 96 µS typical gain providing on-time control proportional to (COMP voltage - 125 mV)."+ },+ {+ "number": "6",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground connection for bypass capacitors, compensation networks, and low-level analog signal returns."+ },+ {+ "number": "7",+ "name": "VINAC",+ "type": "input",+ "description": "Input AC mains voltage sense input with 1.39 V brownout threshold and 440 ms filter delay time."+ },+ {+ "number": "8",+ "name": "HVSEN",+ "type": "input",+ "description": "High voltage output sense for redundant FailSafe OVP with 4.87 V rising threshold; must stay above 0.8 V during normal operation."+ },+ {+ "number": "9",+ "name": "PWMCNTL",+ "type": "tri_state",+ "description": "Open-drain PWM enable output that pulls low when output voltage in valid range and both ZCD inputs switching correctly in two-phase mode."+ },+ {+ "number": "10",+ "name": "CS",+ "type": "input",+ "description": "Current sense input for shunt resistor with -200 mV rising threshold and -15 mV falling threshold for cycle-by-cycle overcurrent protection."+ },+ {+ "number": "11",+ "name": "GDB",+ "type": "output",+ "description": "Gate drive output for phase B power FET with 1 A source and 1.8 A sink capability and 13 V typical high output voltage."+ },+ {+ "number": "12",+ "name": "VCC",+ "type": "power_in",+ "description": "Bias supply input requiring regulated 14-21 V with 6 mA minimum DC capability plus transient gate charge current."+ },+ {+ "number": "13",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground for integrated circuit isolated from analog ground via separate dedicated trace."+ },+ {+ "number": "14",+ "name": "GDA",+ "type": "output",+ "description": "Gate drive output for phase A power FET with 1 A source and 1.8 A sink capability and 13 V typical high output voltage."+ },+ {+ "number": "15",+ "name": "VREF",+ "type": "power_out",+ "description": "Reference voltage output providing 6.0 V regulated supply with 2 mA maximum load current capability."+ },+ {+ "number": "16",+ "name": "ZCDA",+ "type": "input",+ "description": "Zero current detection input for phase A with 0-3 V clamp range, 1.0 V falling threshold, and 1.68 V rising threshold for inductor current decay monitoring."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 36,+ "cost_usd": 0.3814,+ "at": "2026-09-22T21:29:05"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/ucc28061.pdf",+ "pages": 36,+ "sha256": "680a4a083278a849",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}