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ucc28061dr

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Texas Instruments AC-DC Controllers And Regulators, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

componentpower management (pmic)ucc28061drfactory-2.0.0extractor-text
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Contents

README

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UCC28061DR

Texas Instruments · AC-DC Controllers And Regulators · SOIC-16

UCC28061DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ZCDB input Zero current detection input for phase B with 0-3 V clamp range, 1.0 V falling threshold, and 1.68 V rising threshold for inductor current decay monitoring.
2 VSENSE input Output voltage sense input for error amplifier feedback with 6 V reference; pullable low by open-drain logic to disable gate drivers.
3 TSET input Timing resistor connection to AGND that programs on-time factor and minimum switching period proportionally.
4 PHB input Phase B management input; pull high or to VREF for two-phase operation or to ground for single-phase operation.
5 COMP output Error amplifier transconductance output with 96 µS typical gain providing on-time control proportional to (COMP voltage - 125 mV).
6 AGND power_in Analog ground connection for bypass capacitors, compensation networks, and low-level analog signal returns.
7 VINAC input Input AC mains voltage sense input with 1.39 V brownout threshold and 440 ms filter delay time.
8 HVSEN input High voltage output sense for redundant FailSafe OVP with 4.87 V rising threshold; must stay above 0.8 V during normal operation.
9 PWMCNTL tri_state Open-drain PWM enable output that pulls low when output voltage in valid range and both ZCD inputs switching correctly in two-phase mode.
10 CS input Current sense input for shunt resistor with -200 mV rising threshold and -15 mV falling threshold for cycle-by-cycle overcurrent protection.
11 GDB output Gate drive output for phase B power FET with 1 A source and 1.8 A sink capability and 13 V typical high output voltage.
12 VCC power_in Bias supply input requiring regulated 14-21 V with 6 mA minimum DC capability plus transient gate charge current.
13 PGND power_in Power ground for integrated circuit isolated from analog ground via separate dedicated trace.
14 GDA output Gate drive output for phase A power FET with 1 A source and 1.8 A sink capability and 13 V typical high output voltage.
15 VREF power_out Reference voltage output providing 6.0 V regulated supply with 2 mA maximum load current capability.
16 ZCDA input Zero current detection input for phase A with 0-3 V clamp range, 1.0 V falling threshold, and 1.68 V rising threshold for inductor current decay monitoring.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Power Management (PMIC)
Pins 16

CAD (KiCad official)

  • Symbol: UCC28061DR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: ucc28061dr-etched.step / ucc28061dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc28061dr.step / ucc28061dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (36 pp, sha256 680a4a083278a849, retrieved 2026-09-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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PCB Footprint

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Datasheet

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