component
UCC2802QDRQ1
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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UCC2802QDRQ1
Texas Instruments · AC-DC Controllers And Regulators · SOIC-8
UCC2802QDRQ1 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | COMP is the error amplifier output and PWM comparator input; the low-output-impedance 2 MHz error amplifier can both source and sink current, and forcing COMP to GND sets zero duty cycle. |
| 2 | FB | input | FB is the inverting input of the error amplifier, and its trace length and stray capacitance should be kept as small as possible for best stability. |
| 3 | CS | input | CS is the input to the PWM comparator and the over-current comparator, with a 100 ns leading-edge blanking interval after the OUT rising edge and an over-current threshold of 1.5 V. |
| 4 | RC | input | RC is the oscillator timing pin, with the timing resistor connected from REF to RC (10 kΩ to 200 kΩ recommended, never below 10 kΩ) and the timing capacitor from RC to GND (100 pF to 1000 pF recommended), supporting frequencies up to 1 MHz. |
| 5 | GND | power_in | GND is the reference and power ground for all functions, and the datasheet recommends separating the signal return path from the high-current gate-driver path. |
| 6 | OUT | output | OUT is the high-current totem-pole gate driver output, able to drive MOSFET gates with peak current above ±750 mA (±1 A absolute maximum) and held low while VCC is below the UVLO threshold. |
| 7 | VCC | power_in | VCC is the device supply input, normally fed through a current-limiting resistor, with an absolute maximum of 12 V and 30 mA, and an internal zener clamp typically at 13.5 V; bypass to GND with a ceramic capacitor placed close to the pin. |
| 8 | REF | output | REF is the 5 V voltage reference for the error amplifier and other internal functions, requires at least a 0.1 µF ceramic bypass to GND placed close to the pin, is pulled low through 5 kΩ when VCC is between 1 V and the UVLO threshold, and external loads above 2.5 mA need additional bypass. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
UCC2802QDRQ1 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ucc2802qdrq1-etched.step/ucc2802qdrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucc2802qdrq1.step/ucc2802qdrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (47 pp, sha256
f3617bb600d56d65, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).