UCC2802DTR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	COMP	output	COMP is the output of the error amplifier and the input of the PWM comparator, and because the amplifier is internally current-limited, forcing COMP to GND commands zero duty cycle.
2	FB	input	FB is the inverting input of the error amplifier, and its lead length and stray capacitance should be kept as short and small as possible for best stability.
3	CS	input	CS is the input to the PWM and overcurrent current-sense comparators, and internal leading-edge blanking disconnects it from the comparator for 100 ns after the rising edge of OUT.
4	RC	input	RC is the oscillator timing pin, where a resistor from REF to RC sets the charging current and a capacitor from RC to GND sets the frequency, with recommended timing resistors of 10 kΩ to 200 kΩ and timing capacitors of 100 pF to 1000 pF.
5	GND	power_in	GND is the reference ground and power ground for all functions on the part.
6	OUT	output	OUT is a high-current power driver output capable of driving a power MOSFET gate with peak currents exceeding ±750 mA, and it is actively held low when VCC is below the UVLO threshold.
7	VCC	power_in	VCC is the power input of the device, normally fed through a current-limiting resistor, and must be bypassed to GND with a minimum of 1 µF in parallel with a 0.1 µF ceramic capacitor placed close to the device.
8	REF	output	REF is the voltage reference for the error amplifier and other functions, is pulled to ground through 5 kΩ when VCC is between 1 V and the UVLO threshold, and requires a minimum 0.1 µF ceramic bypass capacitor to GND with additional bypassing for external loads above 2.5 mA.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-8
Category	Power Management (PMIC)
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VCC voltage	VCC			12	V	All voltages with respect to GND	6
VCC current	ICC			30	mA		6
OUT current	IOUT	-1		1	A		6
OUT energy (capacitive load)				20	µJ	capacitive load	6
Analog inputs (FB, CS, RC, COMP)		-0.3		6.3	V	6.3 or VCC + 0.3; return the lesser value	6
Power dissipation at TA < 25°C, D package				0.65	W	TA < 25°C, D package	6
Lead temperature, soldering (10 s)				300	°C	10 s	6
Storage temperature	Tstg	-65		150	°C		6
Junction temperature	TJ	-55		150	°C		6
VCC bias supply voltage	VVCC			11	V	from low impedance source	6
Voltage on analog pins	VFB, VCS, VRC, VCOMP	-0.1		6	V	6 or VVCC	6
Gate driver output voltage	VOUT	-0.1			V	max printed as VVCC	6
Supply bias current	IVCC			25	mA		6
Average OUT pin current	IOUT			20	mA		6
REF pin output current	IREF			5	mA		6
Oscillator frequency	fOSC			1	MHz		6
Operating free-air temperature	TA	-40		125	°C		6
Junction-to-ambient thermal resistance	RθJA		117.9		°C/W	D (SOIC) 8 pins	7
Junction-to-case (top) thermal resistance	RθJC(top)		60.8		°C/W	D (SOIC) 8 pins	7
Junction-to-board thermal resistance	RθJB		62.2		°C/W	D (SOIC) 8 pins	7
Junction-to-top characterization parameter	ψJT		14.4		°C/W	D (SOIC) 8 pins	7
Junction-to-board characterization parameter	ψJB		61.7		°C/W	D (SOIC) 8 pins	7
Reference output voltage	VREF	4.925	5	5.075	V	TJ = 25°C, I = 0.2 mA, UCC2800, UCC2801, UCC2802 and UCC2804	7
Load regulation			10	30	mV	0.2 mA < I < 5 mA, UCC280x	7
Line regulation			1.9		mV/V	TJ = 25°C, VCC = 10 V to clamp (IVCC = 25 mA)	7
Line regulation				2.5	mV/V	TJ = -40°C to 125°C, VCC = 10 V to clamp (IVCC = 25 mA), UCC280x	7
Total variation	VREF	4.88	5	5.1	V	UCC2800, UCC2801, UCC2802 and UCC2804; includes temperature stability and load regulation	7
Output short circuit			-5	-35	mA		7
Oscillator frequency	fOSC	40	46	52	kHz	UCC2800, UCC2801, UCC2802 and UCC2804	7
Temperature stability			2.5		%	Ensured by design, not 100% tested in production	7
Amplitude peak-to-peak		2.25	2.4	2.55	V		7
Error amplifier input voltage		2.44	2.5	2.56	V	COMP = 2.5 V, UCC2800, UCC2801, UCC2802 and UCC2804	7
Input bias current		-1		1	µA		7
Open loop voltage gain		60	80		dB		7
COMP sink current			0.3	3.5	mA	FB = 2.7 V, COMP = 1.1 V, UCC280x	7
COMP source current		-0.2	-0.5	-0.8	mA	FB = 1.8 V, COMP = REF, 1.2 V	7
Maximum duty cycle		97	99	100	%	UCC2800, UCC2802 and UCC2803	8
Current sense gain	A	1.1	1.65	1.8	V/V		8
Maximum input signal		0.9	1	1.1	V	COMP = 5 V	8
Input bias current (CS)		-200		200	nA		8
CS blank time		50	100	150	ns		8
Overcurrent threshold		1.42	1.55	1.68	V		8
COMP to CS offset		0.45	0.9	1.35	V	CS = 0 V	8
OUT low level			0.1	0.4	V	I = 20 mA, all parts	8
OUT low level			0.35	0.9	V	I = 200 mA, all parts	8
OUT low level			0.7	1.2	V	I = 20 mA, VCC = 0 V, all parts	8
OUT high VSAT (VCC-OUT)			0.15	0.4	V	I = 20 mA, all parts	8
OUT high VSAT (VCC-OUT)			1	1.9	V	I = 200 mA, all parts	8
Rise time			41	70	ns	CL = 1 nF	8
Fall time			44	75	ns	CL = 1 nF	8
Start threshold		11.5	12.5	13.5	V	UCC2802 and UCC2804	8
Stop threshold		7.6	8.3	9	V	UCC2802 and UCC2804	8
Start to stop hysteresis		3.5	4.2	5.1	V	UCC2802 and UCC2804	8
COMP rise time			4	10	ms	FB = 1.8 V, rise from 0.5 V to REF, 1 V	8
Start-up current			0.1	0.2	mA	VCC < start threshold	8
Operating supply current			0.5	1	mA	FB = 0 V, CS = 0 V	8
VCC internal Zener voltage		12	13.5	15	V	ICC = 10 mA	8

CAD (KiCad official)

Symbol: UCC2802DTR
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: ucc2802dtr-etched.step / ucc2802dtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc2802dtr.step / ucc2802dtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (60 pp, sha256 5b21bde28e34d5ba, retrieved 2026-11-06, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

UCC2802DTR

Verified UCC2802DTR

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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