Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

Download PDF

Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

UCC27614DSGR

Texas Instruments · Gate Drive ICs · WSON-8-EP(2x2)

UCC27614DSGR from Texas Instruments, in a WSON-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IN+	input	Non-inverting PWM input; if not used, connect to VDD, and it withstands -10 V to 30 V (abs max).
2	GND	power_in	Device ground or reference.
3	GND	power_in	Device ground or reference.
4	OUT	output	Output of the driver with typical 10-A source and 10-A sink peak current.
5	OUT	output	Output of the driver with typical 10-A source and 10-A sink peak current.
6	VDD	power_in	Driver bias supply (4.5 V to 26 V recommended, 30 V abs max); bypass with two ceramic capacitors, generally >=1 µF and 0.1 µF, referenced to GND.
7	VDD	power_in	Driver bias supply (4.5 V to 26 V recommended, 30 V abs max); bypass with two ceramic capacitors, generally >=1 µF and 0.1 µF, referenced to GND.
8	IN-	input	Inverting PWM input; if not used, connect to GND, and it withstands -10 V to 30 V (abs max).
9	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WSON-8-EP(2x2)
Category	Power Supply Chip
Pins	9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VDD	-0.3		30	V		4
Output voltage (DC)	VOUT	-0.3			V	max is VDD + 0.3 V	4
Input voltage IN, EN, IN+, IN-		-10		30	V		4
Operating junction temperature (abs max)	TJ	-40		150	°C		4
Storage temperature	Tstg	-65		150	°C		4
Supply voltage	VDD	4.5	12	26	V		4
Input voltage IN, IN+, IN-, EN		-10		26	V		4
Operating junction temperature	TJ	-40		150	°C		4
VDD quiescent supply current	IVDDq		305	500	µA	VIN+/VIN = 3.3 V, VIN- = 0 V, EN=VDD, VDD = 3.4 V	5
VDD static supply current	IVDD		0.64	0.92	mA	VIN+/VIN = 3.3 V, VIN- = 0 V, EN = VDD	5
VDD static supply current	IVDD		0.71	1	mA	VIN+/VIN = 0 V, VIN- = 0 V, EN = VDD	5
VDD disable current	IDIS		0.75	1	mA	VIN+/VIN = 0 V, VIN- = 3.3 V, EN = 0 V	5
VDD UVLO rising threshold	VVDD_ON	3.8	4.1	4.4	V		5
VDD UVLO falling threshold	VVDD_OFF	3.5	3.8	4.1	V		5
Input signal high threshold, output high	VIN_H	1.8	2	2.3	V	Output high, IN- = LOW, EN=HIGH	5
Input signal low threshold, output low	VIN_L	0.8	1	1.2	V	Output low, IN- = LOW, EN=HIGH	5
IN- high threshold, output low	VIN-_H	1.8	2	2.3	V	Output low, IN+ = HIGH, EN = high	5
IN- low threshold, output high	VIN-_L	0.8	1	1.2	V	Output high, IN+ = HIGH, EN = high	5
Enable signal high threshold	VEN_H	1.8	2	2.3	V	Output high, IN+/IN = high, IN- =0 V	5
Enable signal low threshold	VEN_L	0.8	1	1.2	V	Output low, IN+/IN = high, IN- = 0 V	5
OUTH pullup resistance	ROH		2.5	4.5	Ω	IOUT = -50 mA	5
OUTL pulldown resistance	ROL		0.34	0.55	Ω	IOUT = 50 mA	5
Rise time	tR		4.5	6	ns	CLOAD = 1.8 nF, 20% to 80%, VIN = 0 V to 3.3 V	6
Fall time	tF		4	5.5	ns	CLOAD = 1.8 nF, 90% to 10%, VIN = 0 V to 3.3 V	6
Turnon propagation delay	tD1		17.5	27	ns	CLOAD = 1.8 nF, Fsw=500 kHz, 50% duty cycle, TJ = 125°C	6
Turn-off propagation delay	tD2		17.5	27	ns	CLOAD = 1.8 nF, Fsw=500 kHz, 50% duty cycle, TJ = 125°C	6
Enable propagation delay	tPD_EN		17.5	27	ns	CLOAD = 1.8 nF, Fsw=500 kHz, 50% duty cycle, TJ = 125°C	6
Disable propagation delay	tPD_DIS		17.5	27	ns	CLOAD = 1.8 nF, Fsw = 500 kHz, 50% duty cycle, TJ = 125°C	6
VDD UVLO ON delay	tVDD+_OUT		3.2	6	µs	VDD = 0 V to 4.5 V in 100 ns	6
Minimum input pulse width	tPWmin		9	15	ns	CLOAD = 1.8 nF, VIN = 0 V to 3.3 V, Fsw = 500 kHz, Vo > 1.5 V	6
VDD UVLO hysteresis	VVDD_HYS		0.3		V		5
Input signal hysteresis	VIN_HYS		1		V		5
IN pin pulldown resistance	RIN		120		kΩ	IN+/IN = 3.3 V	5
IN- pin pullup resistance	RIN-		200		kΩ	IN- = 0 V	5
EN pin pullup resistance	REN		200		kΩ	EN = 0 V	5
VDD dynamic operating current	IVDDO		4		mA	fSW = 1000 kHz, EN = VDD, VIN+/VIN = 0 V to 3.3 V PWM, VIN- = 0 V	5
Peak output source current	ISRC		10		A	VDD = 12 V, CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz	5
Peak output sink current	ISNK		-10		A	VDD = 12 V, CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz	5
VDD UVLO OFF delay	tVDD-_OUT		7.5		us	VDD = 4.5 V to 3.4 V in 100 ns	6
Junction-to-ambient thermal resistance	RθJA		67.9		°C/W	SON (DSG)	4
Junction-to-case (top) thermal resistance	RθJC(top)		81.1		°C/W	SON (DSG)	4
Junction-to-board thermal resistance	RθJB		33.4		°C/W	SON (DSG)	4
Junction-to-case (bottom) thermal resistance	RθJC(bot)		12.2		°C/W	SON (DSG)	4

CAD (KiCad official)

Symbol: UCC27614DSGR
Footprint: Package_SON:WSON-8-1EP_2x2mm_P0.5mm_EP0.9x1.6mm
3D model: WSON-8-EP(2x2) (KiCad packages3D, STEP)
3D model files: ucc27614dsgr-etched.step / ucc27614dsgr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc27614dsgr.step / ucc27614dsgr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (39 pp, sha256 7a79f2c30f85b692, retrieved 2026-10-22, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF