component
UCC27524AQDRQ1
Public Made by Adomby adom
Texas Instruments Gate Drive ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownUCC27524AQDRQ1
Texas Instruments · Gate Drive ICs · SOIC-8
UCC27524AQDRQ1 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ENA | input | Channel A enable input: biased low to disable the OUTA output regardless of INA state, biased high or left floating to enable it (internally pulled up to VDD via 200kΩ). |
| 2 | INA | input | Channel A non-inverting input; OUTA stays low if INA is unbiased or floating (120kΩ internal pulldown), with 2V typical high and 1V typical low thresholds. |
| 3 | GND | power_in | Ground: all signals are referenced to this pin. |
| 4 | INB | input | Channel B non-inverting input; OUTB stays low if INB is unbiased or floating (120kΩ internal pulldown), with 2V typical high and 1V typical low thresholds. |
| 5 | OUTB | output | Channel B output, capable of 5A peak source and 5A peak sink current. |
| 6 | VDD | power_in | Bias supply input, 4.5V to 18V recommended operating range (20V absolute maximum), with bypass capacitors to GND placed close to the pin. |
| 7 | OUTA | output | Channel A output, capable of 5A peak source and 5A peak sink current. |
| 8 | ENB | input | Channel B enable input: biased low to disable the OUTB output regardless of INB state, biased high or left floating to enable it (internally pulled up to VDD via 200kΩ). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Supply Chip |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD supply voltage | VDD | -0.3 | 20 | V | 5 | ||
| OUTA/OUTB voltage DC | -0.3 | V | DC; max VDD + 0.3 | 5 | |||
| OUTA/OUTB voltage repetitive pulse | -2 | V | repetitive pulse < 200 ns; max VDD + 0.3 | 5 | |||
| Output continuous source/sink current | IOUT_DC | 0.3 | A | 5 | |||
| Output pulsed source/sink current | IOUT_pulsed | 5 | A | 0.5µs | 5 | ||
| INA, INB, ENA, ENB voltage | -5 | 20 | V | 5 | |||
| Operating virtual junction temperature | TJ | -40 | 150 | °C | 5 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| ESD HBM | V(ESD) | -2000 | 2000 | V | AEC Q100-002 | 5 | |
| ESD CDM | V(ESD) | -1000 | 1000 | V | AEC Q100-011 | 5 | |
| Supply voltage | VDD | 4.5 | 12 | 18 | V | 5 | |
| Operating junction temperature | TJ | -40 | 140 | °C | 5 | ||
| Input voltage INA, INB | -2 | 18 | V | 5 | |||
| Enable voltage ENA, ENB | -2 | 18 | V | 5 | |||
| Junction-to-ambient thermal resistance | RθJA | 126.4 | °C/W | D package, 8-pin | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 67 | °C/W | D package | 5 | ||
| Junction-to-board thermal resistance | RθJB | 69.9 | °C/W | D package | 5 | ||
| Junction-to-top characterization parameter | ψJT | 19.2 | °C/W | D package | 5 | ||
| Junction-to-board characterization parameter | ψJB | 69.1 | °C/W | D package | 5 | ||
| VDD quiescent current | IVDDq | 300 | 450 | µA | VINx = 3.3V, VDD = 3.4V, ENx = VDD | 6 | |
| VDD quiescent current | IVDD | 0.6 | 1 | mA | VINx = 3.3V, ENx = VDD | 6 | |
| VDD quiescent current | IVDD | 0.7 | 1 | mA | VINx = 0V, ENx = VDD | 6 | |
| VDD operating current | IVDDO | 3.2 | 3.8 | mA | fSW = 1000kHz, ENx = VDD, VINx = 0V to 3.3V PWM | 6 | |
| VDD disable current | IDIS | 0.8 | 1.1 | mA | VINx = 3.3V, ENx = 0V | 6 | |
| VDD UVLO rising threshold | VVDD_ON | 3.8 | 4.1 | 4.4 | V | 6 | |
| VDD UVLO falling threshold | VVDD_OFF | 3.5 | 3.8 | 4.1 | V | 6 | |
| Input signal high threshold | VINx_H | 1.8 | 2 | 2.3 | V | Output high, ENx = HIGH | 6 |
| Input signal low threshold | VINx_L | 0.8 | 1 | 1.2 | V | Output low, ENx = HIGH | 6 |
| Enable signal high threshold | VENx_H | 1.8 | 2 | 2.3 | V | Output high, INx = HIGH | 6 |
| Enable signal low threshold | VENx_L | 0.8 | 1 | 1.2 | V | Output low, INx = HIGH | 6 |
| Output pull-up resistance | ROH | 5 | 8.5 | Ω | IOUT = -50mA | 6 | |
| Output pull-down resistance | ROL | 0.6 | 1.1 | Ω | IOUT = 50mA | 6 | |
| Rise time | tRx | 6 | 10 | ns | CLOAD = 1.8nF, 20% to 80%, Vin = 0V, 3.3V | 7 | |
| Fall time | tFx | 10 | 14 | ns | CLOAD = 1.8nF, 90% to 10%, Vin = 0V, 3.3V | 7 | |
| Turn-on propagation delay | tD1x | 17 | 27 | ns | CLOAD = 1.8nF, Vin = 0V, 3.3V, Fsw = 500kHz, 50% duty, TJ = 125°C | 7 | |
| Turn-off propagation delay | tD2x | 17 | 27 | ns | CLOAD = 1.8nF, Vin = 0V, 3.3V, Fsw = 500kHz, 50% duty, TJ = 125°C | 7 | |
| Enable propagation delay | tD3x | 17 | 27 | ns | CLOAD = 1.8nF, Vin = 0V, 3.3V, Fsw = 500kHz, 50% duty, TJ = 125°C | 7 | |
| Disable propagation delay | tD4x | 17 | 27 | ns | CLOAD = 1.8nF, Vin = 0V, 3.3V, Fsw = 500kHz, 50% duty, TJ = 125°C | 7 | |
| Delay matching between two channels | tM | 1 | 2 | ns | CLOAD = 1.8nF, Vin = 0V, 3.3V, Fsw = 500kHz, 50% duty, INA = INB, /tRA, tRB/, /tFA, tFB/ | 7 | |
| Minimum input pulse width | tPWmin | 10 | 15 | ns | CL = 1.8nF, Vin = 0V, 3.3V, Fsw = 500kHz, Vo > 1.5V | 7 | |
| Peak output source current | ISRC | 5 | A | VDD = 12V, CVDD = 10µF, CL = 0.1µF, f = 1kHz | 6 | ||
| Peak output sink current | ISNK | -5 | A | VDD = 12V, CVDD = 10µF, CL = 0.1µF, f = 1kHz | 6 | ||
| VDD UVLO hysteresis | VVDD_HYS | 0.3 | V | 6 | |||
| Input signal hysteresis | VINx_HYS | 1 | V | 6 | |||
| INx pin pull-down resistance | RINx | 120 | kΩ | INx = 3.3V | 6 | ||
| Enable signal hysteresis | VENx_HYS | 1 | V | 6 | |||
| EN pin pull-up resistance | RENx | 200 | kΩ | ENx = 0V | 6 |
CAD (KiCad official)
- Symbol:
UCC27524AQDRQ1 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ucc27524aqdrq1-etched.step/ucc27524aqdrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucc27524aqdrq1.step/ucc27524aqdrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (40 pp, sha256
5e85fad81551a14d, retrieved 2026-10-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).