component

UCC27524 Dual Gate Driver

Public Made by Adom

by adom

Dual 5 A high-speed low-side MOSFET/IGBT gate driver with matched delays.

gate-drivermosfet-driverduallow-sidehigh-currenttisoic-8
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Made with kicad-footprint-generator 10.0 · KiCad file format 20260206
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docs ucc27524: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 4d ago
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page.json ucc27524: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 15h ago
README.md ucc27524: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 16d ago
ucc27524-etched.fit.json ucc27524: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 4d ago
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ucc27524-etched.step ucc27524: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 4d ago
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UCC27524

Texas Instruments · Gate Driver · SOIC-8

The UCC27524 is a dual high-speed low-side gate driver that sources and sinks up to 5 A to drive power MOSFETs and IGBTs. Its matched propagation delays, wide supply range, and fast rise/fall times suit switching power supplies, motor drives, and synchronous rectification where two gates must switch quickly and in step.

Pinout

Pin Name Type Function
1 ENA input Enable input for Channel A. Bias LOW to disable OUTA regardless of INA state; bias HIGH or leave floating to enable Channel A. Internally pulled up to VDD for pin-to-pin compatibility with UCC27324 N/C pin.
2 INA input Non-inverting logic input to Channel A. Drives OUTA high when HIGH. OUTA is held LOW if INA is unbiased or floating due to internal pulldown (~120 kΩ). TTL/CMOS thresholds with ~1V hysteresis; can accept -5V (D/DGN pkg).
3 GND power_in Device ground return. All signals and supply voltages are referenced to this pin.
4 INB input Non-inverting logic input to Channel B. Drives OUTB high when HIGH. OUTB is held LOW if INB is unbiased or floating due to internal pulldown (~120 kΩ). TTL/CMOS thresholds with ~1V hysteresis; can accept -5V (D/DGN pkg).
5 OUTB output Gate-drive output for Channel B. Rail-to-rail push-pull driver capable of 5A peak source/sink into MOSFET/IGBT gates. Held LOW during VDD UVLO and when INB is floating.
6 VDD power_in Bias supply input. 4.5V to 18V recommended operating range (20V absolute max). Bypass with a low-ESR ceramic capacitor (typ. 1 µF) directly to GND. UVLO rising threshold ~4.1V.
7 OUTA output Gate-drive output for Channel A. Rail-to-rail push-pull driver capable of 5A peak source/sink into MOSFET/IGBT gates. Held LOW during VDD UVLO and when INA is floating.
8 ENB input Enable input for Channel B. Bias LOW to disable OUTB regardless of INB state; bias HIGH or leave floating to enable Channel B. Internally pulled up to VDD for pin-to-pin compatibility with UCC27324 N/C pin.

Key specifications

Parameter Value
Type Dual low-side gate driver
Peak output current 5 A source/sink
Supply voltage 4.5 V to 18 V
Rise/fall time 7 ns / 6 ns into 1.8 nF
Propagation delay 13 ns typ (matched)
Inputs TTL/CMOS compatible
Operating temperature -40 C to 140 C

Ordering variants

Same part, different packaging or reel option.

  • UCC27524D
  • UCC27524DGN
  • UCC27524DSD

CAD (KiCad official)

  • Symbol: ucc27524.kicad_sym
  • Footprint: ucc27524.kicad_mod
  • 3D model: SOIC-8 body from KiCad Package_SO/SOIC-8_3.9x4.9mm_P1.27mm.
  • 3D model files: ucc27524-etched.step / ucc27524-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc27524.step / ucc27524.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (50 pp, sha256 57d2e9b2b8063627, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF