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Contents

README

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UCC27423DR

Texas Instruments · Pre-ordered Chips · SOIC-8

UCC27423DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ENBA input Enable input for driver A with logic-compatible threshold and hysteresis, internally pulled up to VDD with 100 kΩ for active-high operation; output is low when disabled regardless of input state, and it can be left open.
2 INA input Input signal of driver A with logic-compatible threshold and hysteresis; if unused it must be tied to VDD or GND and not left floating.
3 GND power_in Common ground, which should be connected very closely to the source of the power MOSFET being driven.
4 INB input Input signal of driver B with logic-compatible threshold and hysteresis; if unused it must be tied to VDD or GND and not left floating.
5 OUTB output Driver output B, whose output stage can provide 4 A of drive current to the gate of a power MOSFET.
6 VDD power_in Supply voltage and power input connection for the device, with a recommended operating range of 4 V to 15 V.
7 OUTA output Driver output A, whose output stage can provide 4 A of drive current to the gate of a power MOSFET.
8 ENBB input Enable input for driver B with logic-compatible threshold and hysteresis, internally pulled up to VDD with 100 kΩ for active-high operation; output is low when disabled regardless of input state, and it can be left open.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD -0.3 16 V 5
Output current DC (OUTA, OUTB) IOUT_DC 0.2 A DC 5
Output current pulsed (OUTA, OUTB) IOUT_PULSED 4.5 A Pulsed, (0.5 μs) 5
Input voltage (INA, INB) VIN -5 6 V max 6 or VDD + 0.3 (whichever is larger) 5
Enable voltage (ENBA, ENBB) -0.3 6 V max 6 or VDD + 0.3 (whichever is larger) 5
Power dissipation D package 650 mW TA = 25°C, D package 5
Junction operating temperature TJ -55 150 °C 5
Lead temperature 300 °C soldering, 10 s 5
Storage temperature Tstg -65 150 °C 5
ESD HBM V(ESD) -2000 2000 V Human body model, per AEC Q100-002 5
ESD CDM V(ESD) -1000 1000 V Charged device model, per AEC Q100-011 5
Supply voltage VDD 4 15 V 5
Input voltage INA and INB -2 15 V 5
Enable voltage ENA and ENB 0 15 V 5
Operating junction temperature TJ -40 125 °C 5
Junction-to-ambient thermal resistance RθJA 107.3 °C/W D (SOIC) 8 pins 5
Junction-to-case (top) thermal resistance RθJC(top) 52.2 °C/W D (SOIC) 8 pins 5
Junction-to-board thermal resistance RθJB 47.3 °C/W D (SOIC) 8 pins 5
Junction-to-top characterization parameter ψJT 10.2 °C/W D (SOIC) 8 pins 5
Junction-to-board characterization parameter ψJB 46.8 °C/W D (SOIC) 8 pins 5
Logic 1 input threshold VIN_H 1.6 2.2 2.5 V INPUT (INA, INB) 6
Logic 0 input threshold VIN_L 0.8 1.2 1.5 V INPUT (INA, INB) 6
Input current -10 0 10 μA 0 V ≤ VIN ≤ VDD 6
Output current 4 A VDD = 14 V (not tested in production) 6
Output resistance high ROH 1.2 2.5 Ω IOUT = -10 mA 6
Output resistance low ROL 0.7 1.2 Ω IOUT = 10 mA 6
Rise time (OUTA, OUTB) tr 20 40 ns CLOAD = 1.8 nF 6
Fall time (OUTA, OUTB) tf 15 40 ns CLOAD = 1.8 nF 6
Delay, IN rising (IN to OUT) td1 25 40 ns CLOAD = 1.8 nF 6
Delay, IN falling (IN to OUT) td2 35 50 ns CLOAD = 1.8 nF 6
Enable high-level input voltage VIN_H 1.7 2.4 2.9 V LO to HI transition 6
Enable low-level input voltage VIN_L 1.1 1.8 2.2 V HI to LO transition 6
Enable hysteresis 0.15 0.55 0.9 V 6
Enable impedance RENB 75 100 140 kΩ VDD = 14 V, ENB = GND 6
Enable propagation delay time tD3 30 60 ns CLOAD = 1.8 nF (see Figure 6-3) 6
Enable propagation delay time tD4 100 150 ns CLOAD = 1.8 nF (see Figure 6-3) 6
Static operating current UCC27423 IDD 900 1350 μA VDD = 15 V, ENBA = ENBB = 15 V, INA = 0 V, INB = 0 V 6
Static operating current UCC27423 IDD 750 1100 μA VDD = 15 V, ENBA = ENBB = 15 V, INA = 0 V, INB = HIGH 6
Static operating current UCC27423 IDD 600 900 μA VDD = 15 V, ENBA = ENBB = 15 V, INA = HIGH, INB = HIGH 6
Disabled operating current IDD 300 450 μA All disabled, VDD = 15 V, ENBA = ENBB = 0 V, INA = 0 V, INB = 0 V 6
Disabled operating current IDD 450 700 μA All disabled, VDD = 15 V, ENBA = ENBB = 0 V, INA = 0 V, INB = HIGH 6
Disabled operating current IDD 600 900 μA All disabled, VDD = 15 V, ENBA = ENBB = 0 V, INA = HIGH, INB = HIGH 6

CAD (KiCad official)

  • Symbol: UCC27423DR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ucc27423dr-etched.step / ucc27423dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc27423dr.step / ucc27423dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (44 pp, sha256 a4843244d93d28b0, retrieved 2026-10-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF