# UCC27301ADR

**Texas Instruments** · Global Sourcing Parts · SOIC-8

UCC27301ADR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive supply to the low-side gate driver, to be decoupled to VSS (GND) with a typical 0.22µF to 4.7µF capacitor. |
| 2 | HB | power_in | High-side bootstrap supply; the bootstrap diode is on-chip, and the positive side of an external bootstrap capacitor, typically 0.022µF to 0.1µF, connects to this pin. |
| 3 | HO | output | High-side output that connects to the gate of the high-side power MOSFET. |
| 4 | HS | power_in | High-side source connection that connects to the source of the high-side power MOSFET and to the negative side of the bootstrap capacitor. |
| 5 | HI | input | High-side input; if the source impedance exceeds 100Ω, a bypass capacitor of about 1nF to 10nF should be added from HI to VSS. |
| 6 | LI | input | Low-side input; if the source impedance exceeds 100Ω, a bypass capacitor of about 1nF to 10nF should be added from LI to VSS. |
| 7 | VSS | power_in | Negative supply terminal for the device, generally grounded. |
| 8 | LO | output | Low-side output that connects to the gate of the low-side power MOSFET. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Global Sourcing Parts |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | -0.3 |  | 20 | V |  | 5 |
| Input voltages on HI and LI | VHI, VLI | -10 |  | 20 | V |  | 5 |
| Output voltage on LO, DC | VLO | -0.3 |  |  | V | DC | 5 |
| Output voltage on LO, repetitive pulse | VLO | -2 |  |  | V | Repetitive pulse < 100 ns | 5 |
| Voltage on HS, DC | VHS | -1 |  | 120 | V | DC | 5 |
| Voltage on HS, repetitive pulse | VHS |  |  | 120 | V | Repetitive pulse < 100 ns | 5 |
| Voltage on HB | VHB | -0.3 |  | 120 | V |  | 5 |
| Voltage on HB-HS |  | -0.3 |  | 20 | V |  | 5 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 5 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 5 |
| Supply voltage | VDD | 8 | 12 | 17 | V |  | 5 |
| Voltage on HS | VHS | -1 |  | 105 | V |  | 5 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 5 |
| IDD VDD quiescent current | IDD |  | 0.11 | 0.19 | mA | VLI = VHI = 0 V, VEN = 3V | 6 |
| IDDO VDD operating current | IDDO |  | 1.4 | 3 | mA | f = 500 kHz, CLOAD = 0, VEN = 3V | 6 |
| IHB Boot voltage quiescent current | IHB |  | 0.065 | 0.12 | mA | VLI = VHI = 0 V, VEN = 3V | 6 |
| IHBO Boot voltage operating current | IHBO |  | 1.3 | 3 | mA | f = 500 kHz, CLOAD = 0, VEN = 3V | 6 |
| IHBS HB to VSS quiescent current | IHBS |  | 0.0005 | 1 | μA | VHS = VHB = 105 V, VEN = 3V | 6 |
| IHBSO HB to VSS operating current | IHBSO |  | 0.03 | 1 | mA | f = 500 kHz, CLOAD = 0, VEN = 3V | 6 |
| Input voltage high threshold (HI) | VHIT_HI | 1.7 | 2.3 | 2.55 | V |  | 6 |
| Input voltage high threshold (LI) | VHIT_LI | 1.7 | 2.3 | 2.55 | V |  | 6 |
| Input voltage low threshold (HI) | VLIT_HI | 1.2 | 1.6 | 1.9 | V |  | 6 |
| Input voltage low threshold (LI) | VLIT_LI | 1.2 | 1.6 | 1.9 | V |  | 6 |
| Input pulldown resistance (HI) | RIN_HI |  | 68 |  | kΩ | VIN = 3V | 6 |
| Input pulldown resistance (LI) | RIN_LI |  | 68 |  | kΩ | VIN = 3V | 6 |
| VDD rising threshold | VDDR | 6.2 | 7 | 7.8 | V |  | 6 |
| VHB rising threshold | VHBR | 5.6 | 6.7 | 7.9 | V |  | 6 |
| Low-current forward voltage | VF |  | 0.65 | 0.85 | V | I VDD - HB = 100 μA | 6 |
| High-current forward voltage | VFI |  | 0.9 | 1.05 | V | I VDD - HB = 100 mA | 6 |
| Dynamic resistance, ΔVF/ΔI | RD | 0.3 | 0.55 | 0.85 | Ω | I VDD - HB = 160 mA and 180 mA | 6 |
| Low level output voltage (LO) | VLOL |  | 0.07 | 0.19 | V | ILO = 100 mA | 6 |
| High level output voltage (LO) | VLOH |  | 0.11 | 0.29 | V | ILO = -100 mA, VLOH = VDD, VLO | 7 |
| Low level output voltage (HO) | VHOL |  | 0.07 | 0.19 | V | IHO = 100 mA | 7 |
| High level output voltage (HO) | VHOH |  | 0.11 | 0.29 | V | IHO = -100 mA, VHOH = VHB- VHO | 7 |
| VLI falling to VLO falling | tDLFF | 10 | 19 | 30 | ns | CLOAD = 0 pF, from VLIT of LI to 90% of LO falling | 7 |
| VHI falling to VHO falling | tDHFF | 10 | 19 | 30 | ns | CLOAD = 0 pF, from VLIT of HI to 90% of HO falling | 7 |
| VLI rising to VLO rising | tDLRR | 10 | 20 | 42 | ns | CLOAD = 0 pF, from VHIT of LI to 10% of LO rising | 7 |
| VHI rising to VHO rising | tDHRR | 10 | 20 | 42 | ns | CLOAD = 0 pF, CLOAD = 0 pF, from VHIT of HI to 10% of HO rising | 7 |
| Delay matching, LI ON / HI OFF (TJ = 25°C) | tMON |  | 4 | 9.5 | ns | TJ = 25°C, from 10% of LO rising to 90% of HO falling | 7 |
| Delay matching, LI ON / HI OFF (TJ = -40°C to 150°C) | tMON |  | 4 | 17 | ns | TJ = -40°C to 150°C, from 10% of LO rising to 90% of HO falling | 7 |
| Delay matching, LI OFF / HI ON (TJ = 25°C) | tMOFF |  | 4 | 9.5 | ns | TJ = 25°C, from 90% of LO falling to 10% of HO rising | 7 |
| Delay matching, LI OFF / HI ON (TJ = -40°C to 150°C) | tMOFF |  | 4 | 17 | ns | TJ = -40°C to 150°C, from 90% of LO falling to 10% of HO rising | 7 |
| LO rise time (3 V to 9 V) | tR_LO_p1 |  | 0.27 | 0.6 | μs | CLOAD = 0.1 μF, (3V to 9V) | 7 |
| HO rise time (3 V to 9 V) | tR_HO_p1 |  | 0.27 | 0.6 | μs | CLOAD = 0.1 μF, (3V to 9V) | 7 |
| LO fall time (9 V to 3 V) | tF_LO_p1 |  | 0.16 | 0.4 | μs | CLOAD = 0.1 μF, (9V to 3V) | 7 |
| HO fall time (9 V to 3 V) | tF_HO_p1 |  | 0.16 | 0.4 | μs | CLOAD = 0.1 μF, (9V to 3V) | 7 |
| Voltage slew rate on HS | SRHS |  | 50 |  | V/ns |  | 5 |
| Junction-to-ambient thermal resistance | RθJA |  | 112.5 |  | °C/W | D (SOIC) 8-pin package | 5 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 52.1 |  | °C/W | D (SOIC) 8-pin package | 5 |
| Junction-to-board thermal resistance | RθJB |  | 59.6 |  | °C/W | D (SOIC) 8-pin package | 5 |
| Junction-to-top characterization parameter | ψJT |  | 7 |  | °C/W | D (SOIC) 8-pin package | 5 |
| Junction-to-board characterization parameter | ψJB |  | 58.7 |  | °C/W | D (SOIC) 8-pin package | 6 |
| VDD threshold hysteresis | VDDHYS |  | 0.5 |  | V |  | 6 |
| VHB threshold hysteresis | VHBHYS |  | 1.1 |  | V |  | 6 |
| Peak pullup current (LO) |  |  | 3.7 |  | A | VLO = 0 V | 7 |
| Peak pulldown current (LO) |  |  | 4.5 |  | A | VLO = 12 V | 7 |
| LO rise time | tR_LO |  | 7.2 |  | ns | CLOAD = 1000 pF, from 10% to 90% | 7 |
| HO rise time | tR_HO |  | 7.2 |  | ns | CLOAD = 1000 pF, from 10% to 90% | 7 |
| LO fall time | tF_LO |  | 5.5 |  | ns | CLOAD = 1000 pF, from 90% to 10% | 7 |
| HO fall time | tF_HO |  | 5.5 |  | ns | CLOAD = 1000 pF, from 90% to 10% | 7 |

## CAD (KiCad official)

- Symbol: `UCC27301ADR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ucc27301adr-etched.step` / `ucc27301adr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ucc27301adr.step` / `ucc27301adr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/ucc27301a.pdf) (37 pp, sha256 `1dffd70d4589f012`, retrieved 2026-10-20, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ucc27301adr-datasheet.pdf)