# UCC27200DR

**Texas Instruments** · Gate Drivers · SOIC-8

UCC27200DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive supply to the lower gate driver; decouple to VSS (GND) with a typical capacitor range of 0.22μF to 1μF. |
| 2 | HB | power_in | High-side bootstrap supply; the bootstrap diode is on-chip but an external bootstrap capacitor is required, typically 0.022μF to 0.1μF depending on the high-side MOSFET gate charge. |
| 3 | HO | output | High-side output that connects to the gate of the high-side power MOSFET. |
| 4 | HS | passive | High-side source connection that connects to the source of the high-side power MOSFET and to the negative side of the bootstrap capacitor. |
| 5 | HI | input | High-side input that controls the high-side driver. |
| 6 | LI | input | Low-side input that controls the low-side driver. |
| 7 | VSS | power_in | Negative supply terminal for the device, generally grounded and used as the reference for all voltages. |
| 8 | LO | output | Low-side output that connects to the gate of the low-side power MOSFET. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Motor Driver ICs |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD Supply voltage | VDD | -0.3 |  | 20 | V |  | 4 |
| Input voltages on HI and LI | VHI, VLI | -0.3 |  | 20 | V |  | 4 |
| Output voltage on LO | VLO | -0.3 |  |  | V | DC; maximum printed as VDD + 0.3 | 4 |
| Output voltage on LO | VLO | -2 |  |  | V | Repetitive pulse < 100 ns; maximum printed as VDD + 0.3 | 4 |
| Voltage on HS | VHS | -1 |  | 120 | V | DC | 4 |
| Voltage on HS | VHS | -5 |  | 120 | V | Repetitive pulse < 100 ns | 4 |
| Voltage on HB | VHB | -0.3 |  | 120 | V |  | 4 |
| Voltage on HB-HS | VHB-HS | -0.3 |  | 20 | V |  | 4 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 4 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 4 |
| VDD Supply voltage | VDD | 8 | 12 | 17 | V |  | 4 |
| Voltage on HS | VHS | -1 |  | 105 | V |  | 4 |
| Voltage on HS (repetitive pulse) | VHS | -5 |  | 110 | V | repetitive pulse < 100 ns | 4 |
| Voltage on HB | VHB |  |  | 115 | V | minimum printed as VHS + 8.0 | 4 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 4 |
| IDD VDD quiescent current | IDD |  | 0.11 | 0.8 | mA | VLI = VHI = 0 V | 5 |
| IDDO VDD operating current | IDDO |  | 1 | 3 | mA | f = 500 kHz, CLOAD = 0 | 5 |
| IHB Boot voltage quiescent current | IHB |  | 0.065 | 0.8 | mA | VLI = VHI = 0 V | 5 |
| IHBO Boot voltage operating current | IHBO |  | 0.9 | 3 | mA | f = 500 kHz, CLOAD = 0 | 5 |
| IHBS HB to VSS quiescent current | IHBS |  | 0.0005 | 1 | μA | VHS = VHB = 105 V | 5 |
| Input voltage high threshold (UCC27200) | VHIT |  | 6 | 8 | V |  | 5 |
| Input voltage low threshold (UCC27200) | VLIT | 3 | 5.6 |  | V |  | 5 |
| Input pulldown resistance (UCC27200) | RIN | 100 | 200 | 350 | kΩ | VIN = 3V | 5 |
| VDD rising threshold | VDDR | 6.2 | 7.1 | 7.8 | V |  | 5 |
| VHB rising threshold | VHBR | 5.8 | 6.7 | 7.2 | V |  | 5 |
| Low-current forward voltage | VF |  | 0.65 | 0.85 | V | I VDD - HB = 100 μA | 5 |
| High-current forward voltage | VFI |  | 0.85 | 1.1 | V | I VDD - HB = 100 mA | 5 |
| Dynamic resistance ΔVF/ΔI | RD |  | 0.65 | 1 | Ω | I VDD - HB = 120 mA and 100 mA | 5 |
| LO Low level output voltage | VLOL |  | 0.1 | 0.4 | V | ILO = 100 mA | 5 |
| LO High level output voltage | VLOH |  | 0.13 | 0.42 | V | ILO = -100 mA, VLOH = VDD, VLO | 5 |
| HO Low level output voltage | VHOL |  | 0.1 | 0.4 | V | IHO = 100 mA | 5 |
| HO High level output voltage | VHOH |  | 0.13 | 0.42 | V | IHO = -100 mA, VHOH = VHB- VHO | 5 |
| tDLFF VLI falling to VLO falling | tDLFF |  | 22 | 50 | ns | CLOAD = 0 pF, from VLIT of LI to 90% of LO falling | 6 |
| tDHFF VHI falling to VHO falling | tDHFF |  | 22 | 50 | ns | CLOAD = 0 pF, from VIT of HI to 90% of HO falling | 6 |
| tDLRR VLI rising to VLO rising | tDLRR |  | 22 | 50 | ns | CLOAD = 0 pF, from VHIT of LI to 10% of LO rising | 6 |
| tDHRR VHI rising to VHO rising | tDHRR |  | 22 | 50 | ns | CLOAD = 0 pF, from VHIT of HI to 10% of HO rising | 6 |
| Delay matching LI ON, HI OFF | tMON |  | 1 | 7 | ns | LI ON, HI OFF | 6 |
| Delay matching LI OFF, HI ON | tMOFF |  | 1 | 7 | ns | LI OFF, HI ON | 6 |
| LO rise time (3 V to 9 V) | tR_LO_p1 |  | 0.26 | 0.6 | μs | CLOAD = 0.1 μF, (3V to 9V) | 6 |
| HO rise time (3 V to 9 V) | tR_HO_p1 |  | 0.26 | 0.6 | μs | CLOAD = 0.1 μF, (3V to 9V) | 6 |
| LO fall time (9 V to 3 V) | tF_LO_p1 |  | 0.22 | 0.6 | μs | CLOAD = 0.1 μF, (9V to 3V) | 6 |
| HO fall time (9 V to 3 V) | tF_HO_p1 |  | 0.22 | 0.6 | μs | CLOAD = 0.1 μF, (9V to 3V) | 6 |
| Junction-to-ambient thermal resistance (D SOIC) | RθJA |  | 112.5 |  | °C/W |  | 4 |
| Junction-to-case (top) thermal resistance (D SOIC) | RθJC(top) |  | 52.1 |  | °C/W |  | 4 |
| Junction-to-board thermal resistance (D SOIC) | RθJB |  | 59.6 |  | °C/W |  | 4 |
| Junction-to-top characterization parameter (D SOIC) | ψJT |  | 7 |  | °C/W |  | 4 |
| Junction-to-board characterization parameter (D SOIC) | ψJB |  | 58.7 |  | °C/W |  | 4 |

## CAD (KiCad official)

- Symbol: `UCC27200DR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ucc27200dr-etched.step` / `ucc27200dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ucc27200dr.step` / `ucc27200dr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/ucc27200.pdf) (44 pp, sha256 `c05707c37ae48a8a`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ucc27200dr-datasheet.pdf)