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UCC24650DBVR

Public Made by Adom

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Texas Instruments AC-DC Controllers & Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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UCC24650DBVR

Texas Instruments · AC-DC Controllers & Regulators · SOT-23-5

UCC24650DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Bias supply input (4.5 V to 28 V operating) that is continuously monitored for a VDD droop of approximately 3% from the previously sampled level, and the device is disabled below the UVLO threshold.
2 GND power_in Ground reference for the controller and low-side return for the WAKE output; return AC decoupling capacitors close to this pin.
3 ENS output Open-drain MOSFET enable output for a secondary circuit that goes low-impedance to GND after 63 consecutive switching periods longer than tDISS (177 µs typ) and returns to high-impedance after 32 cumulative cycles shorter than tENS (57 µs typ); connect to GND if unused (absolute max 7 V, 0.5 mA sink).
4 N/C unconnected No internal electrical connection.
5 WAKE bidirectional Connects across the ground-referenced rectifier on the transformer secondary as an input monitoring primary-side switching pulses (55 mV threshold) and as an output injecting current-limited 1 µs pulses at 33 kHz when VDD droops to 97% of the last sample; rated up to 230 V absolute max.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Supply Chip
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply current IVDD28 43 63 83 µA VVDD = 28 V, VWAKE = 28 V 5
Supply current IVDD5 30 41 52 µA VVDD = 5 V, VWAKE = 5 V 5
UVLO turn-on voltage at VDD VUVLO(on) 3.6 4 4.4 V VVDD rising threshold 5
UVLO hysteresis VUVLO(hyst) 170 250 330 mV VUVLO(on), VVDD falling threshold 5
PCD voltage threshold VPCD 10 55 100 mV VWAKE high to low 5
Input bias current, out of pin IWAKE 0 0.1 µA VWAKE = 0 V 5
Input leakage current, into pin, cool IWAKE(lkg)cool 0 0.2 µA VWAKE = 200 V, -40°C ≤ TJ ≤ 85°C 5
Input leakage current, into pin, hot IWAKE(lkg)hot 0 3 µA VWAKE = 200 V, 85°C ≤ TJ ≤ 125°C 5
Droop threshold, cool temperature range ΔVVDD5(cool) -3.2 -2.77 -2.3 % VVDD falling from 5 V, dv/dt = -250 V/s, -40°C ≤ TJ ≤ 85°C 5
Wake-up droop threshold, hot temperature range ΔVVDD5(hot) -4 -2.74 -1.5 % VVDD falling from 5 V, dv/dt = -250 V/s, 85°C ≤ TJ ≤ 125°C 5
Wake-up droop threshold, full temperature range ΔVVDD28 -3.2 -2.7 -2.3 % VVDD falling from 28 V, dv/dt = -250 V/s 5
Wake-up drive current, room temperature IWAKE(on)25 20 27 mA VWAKE = 4 V, TJ = 25°C 5
Wake-up current limit IWAKELMT 35 48 60 mA VVDD = 28 V, VWAKE = 28 V 5
ENS switch leakage current IENS(lkg) 0 0.1 µA VENS = 5 V, off-state 5
ENS switch on-resistance RENS(RDS(on)) 1.3 2.7 5 kΩ IENS = 100 µA, on-state 5
PCD minimum time for VWAKE < VPCD tPCD(min) 350 500 650 ns 6
PCD maximum period for ΔVVDD tSW(max) 40 ms 6
Wake-up pulse width tWAKE 0.7 1 1.3 µs ΔVVDD ≥ -5% after PCD 6
Wake-up repeat period tWAKE(rep) 21 30 39 µs ΔVVDD ≥ -5% after PCD 6
Qualifying tSW to enable secondary circuit tENS 40 57 74 µs WAKE input toggling 6
Cumulative cycles to enable secondary circuit NENS 32 cycles tSW < tENS 6
Qualifying tSW to disable secondary circuit tDISS 124 177 230 µs WAKE input toggling 6
Consecutive cycles to disable secondary circuit NDISS 63 cycles tSW > tDISS 6
Input voltage VCC VCC -0.5 30 V 4
Input voltage WAKE WAKE 230 V 4
Input voltage ENS ENS -0.5 7 V 4
Source current WAKE 10 mA 4
Source current ENS 1 mA 4
Sink current ENS 0.5 mA 4
Operating junction temperature TJ -55 150 °C 4
Lead temperature Tlead 260 °C 0.6 mm from case for 10 s 4
Storage temperature Tstg -65 150 °C 4
ESD HBM, all pins except pin 5 V(ESD) -2000 2000 V ANSI/ESDA/JEDEC JS-001 4
ESD HBM, pin 5 V(ESD) -1500 1500 V ANSI/ESDA/JEDEC JS-001 4
ESD CDM, all pins V(ESD) -1000 1000 V JESD22-C101 4
Bias-supply operating voltage VVDD 4.5 28 V 4
WAKE pin voltage VWAKE 200 V 4
ENS pin voltage VENS 0 6 V 4
Power cycle detect interval tPCD 40 ms 4
Operating junction temperature range TJ -40 125 °C 4
Junction-to-ambient thermal resistance RθJA 200.2 °C/W DBV, 5 pins 4
Junction-to-case (top) thermal resistance RθJC(top) 125.5 °C/W DBV, 5 pins 4
Junction-to-board thermal resistance RθJB 35.8 °C/W DBV, 5 pins 4
Junction-to-top characterization parameter ψJT 18.4 °C/W DBV, 5 pins 4
Junction-to-board characterization parameter ψJB 35 °C/W DBV, 5 pins 4

CAD (KiCad official)

  • Symbol: UCC24650DBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: ucc24650dbvr-etched.step / ucc24650dbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc24650dbvr.step / ucc24650dbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (28 pp, sha256 9e4a80fc4ec1a147, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF