component
UCC24624DR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"number": "5",
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"number": "7",
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"type": "power_in",
"description": "Input to the internal linear regulator, connected to the output voltage when that voltage is below 24.75 V, with a series resistor required above 24.75 V to limit the internal clamp current."
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{
"number": "8",
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"name": "Junction temperature (absolute max)",
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"conditions": "Human body model, per ANSI/ESDA/JEDEC JS-001",
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{
"name": "VDD current, REG under voltage",
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"typ": 180,
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"conditions": "VVDD = 5 V, 25℃",
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{
"name": "VDD clamp voltage",
"symbol": "VDDCLAMP",
"kind": "electrical",
"unit": "V",
"min": 24.75,
"typ": 27.5,
"max": 29.5,
"conditions": "IVDD = 15 mA",
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{
"name": "REG turn-on threshold",
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"name": "REG turn-off threshold",
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{
"name": "REG UVLO hysteresis",
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"conditions": "VVD1 or VVD2 falling",
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{
"name": "SR turn-off threshold",
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"min": 2,
"typ": 10.5,
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"conditions": "VVD1 or VVD2 rising",
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{
"name": "VSS pin offset current for turn-off threshold adjustment",
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"unit": "µA",
"min": 260,
"typ": 330,
"max": 400,
"conditions": "",
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{
"name": "Low-level regulation threshold",
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"unit": "mV",
"min": -80,
"typ": -35,
"max": 0,
"conditions": "",
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{
"name": "High-level regulation threshold",
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"min": -165,
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{
"name": "SR turn-on re-arming threshold",
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"min": 1.4,
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{
"name": "Bias current on VD1 or VD2",
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"min": -10,
"typ": 0,
"max": 0.5,
"conditions": "VVD1 = VVD2 = -150 mV",
"source_page": 6,
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{
"name": "VG pull-up resistance",
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{
"name": "VG pull-down resistance",
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{
"name": "VG high clamp level",
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{
"name": "VG output low voltage, VDD low bias",
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"min": 1,
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"conditions": "VVDD = 4 V, IVG = 25 mA",
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"name": "VG output low voltage",
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{
"name": "VG maximum source current",
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"name": "VG maximum sink current",
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{
"name": "REG pin regulation level",
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"name": "Load regulation on REG",
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{
"name": "REG drop out on passthrough mode",
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{
"name": "REG short circuit current",
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"typ": 9.5,
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"conditions": "VVDD = 12 V, VREG = 0 V",
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{
"name": "REG current limit",
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"typ": 60,
"max": 95,
"conditions": "VVDD = 12 V, VREG = 8 V",
"source_page": 6,
"source": "datasheet"
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{
"name": "SR turn-on propagation delay, both channels",
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"typ": 155,
"max": 225,
"conditions": "VVD1, VVD2 moves from 4.7 V to -0.5 V in 5 ns",
"source_page": 7,
"source": "datasheet"
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"name": "SR turn-off propagation delay, both channels",
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"conditions": "VVD1, VVD2 moves from -0.5 V to 4.7 V in 5 ns",
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"name": "VVG1, VVG2 rise time",
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"conditions": "10% to 90%, VVDD = 12 V, CVG = 6.8 nF",
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{
"name": "VVG1, VVG2 fall time",
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