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UCC24624DR

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Texas Instruments DC-DC Converters, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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UCC24624DR

Texas Instruments · DC-DC Converters · SOIC-8

UCC24624DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VG1 output Gate drive output for the channel 1 SR MOSFET, delivering 1.5-A peak source and 4-A peak sink current into a large N-channel MOSFET through a small series resistor.
2 PGND power_in Power return pin for the IC bias current and high peak gate-driver current, which must connect directly to the SR MOSFET source pins.
3 REG power_out Internal linear regulator output that generates a well-regulated 11-V bias rail, requiring a 2.2-µF bypass capacitor from REG to PGND.
4 VD1 input Channel 1 SR MOSFET drain voltage sensing input, rated for -0.7 V to 230 V, which should be routed to avoid shared power-path parasitic inductance.
5 VSS power_in Sense input for the voltage drop across both SR MOSFETs, shared by both channels, where an optional resistor to the MOSFET source adjusts the turn-off threshold.
6 VD2 input Channel 2 SR MOSFET drain voltage sensing input, rated for -0.7 V to 230 V, which should be routed to avoid shared power-path parasitic inductance.
7 VDD power_in Input to the internal linear regulator, connected to the output voltage when that voltage is below 24.75 V, with a series resistor required above 24.75 V to limit the internal clamp current.
8 VG2 output Gate drive output for the channel 2 SR MOSFET, delivering 1.5-A peak source and 4-A peak sink current into a large N-channel MOSFET through a small series resistor.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (VDD) VVDD 4.25 26 V Over operating free-air temperature range 5
Voltage on sensing pins VVD1, VVD2 -0.5 200 V Over operating free-air temperature range 5
Switching frequency fSW 625 kHz Over operating free-air temperature range 5
Junction temperature (recommended) TJ -40 125 °C Over operating free-air temperature range 5
Input voltage VDD (absolute max) VDD -0.3 28 V 4
Input voltage VD1, VD2 (absolute max) VD1, VD2 -0.7 230 V 4
Input voltage VD1, VD2 transient VD1, VD2 -2 230 V For IVD1, IVD2 ≤ -10 mA and less than 300 ns 4
Output voltage VG1, VG2 (absolute max) VG1, VG2 -0.3 V Max printed as VREG+0.7 4
REG pin voltage (absolute max) 13.5 V 4
Peak output current VG1 or VG2 -4 4 A Pulsed, tPULSE ≤ 4 ms, duty cycle ≤ 1% 4
Junction temperature (absolute max) TJ -40 125 °C 4
Storage temperature Tstg -65 150 °C 4
ESD HBM (all pins except 4 and 6) V(ESD) -2000 2000 V Human body model, per ANSI/ESDA/JEDEC JS-001 4
ESD HBM (pins 4 and 6) V(ESD) -1000 1000 V Human body model, per ANSI/ESDA/JEDEC JS-001; pins VD1 and VD2 4
ESD CDM (all pins) V(ESD) -500 500 V Charged device model, per JEDEC JESD22-C101 4
VDD current, REG under voltage IVDDSTART 5 150 275 µA VVDD = 4 V, VVD1 = VVD2 = 0 V 6
VDD current, run IVDDRUN 0.77 1.1 1.5 mA VVDD = 12 V 6
VDD current, run IVDDRUN 0.7 1 1.5 mA VVDD = 5 V 6
VDD current, standby mode IVDDSTBY 110 180 200 µA VVDD = 12 V, 25℃ 6
VDD current, standby mode IVDDSTBY 100 180 200 µA VVDD = 5 V, 25℃ 6
VDD clamp voltage VDDCLAMP 24.75 27.5 29.5 V IVDD = 15 mA 6
REG turn-on threshold VREGON 4.1 4.5 4.8 V 6
REG turn-off threshold VREGOFF 3.63 4 4.25 V 6
REG UVLO hysteresis VREGHYST 0.45 0.5 0.555 V VREGHYST = VREGON, VREGOFF 6
SR turn-on threshold VTHVGON -435 -265 -160 mV VVD1 or VVD2 falling 6
SR turn-off threshold VTHVGOFF 2 10.5 18 mV VVD1 or VVD2 rising 6
VSS pin offset current for turn-off threshold adjustment IVS_OFFSET 260 330 400 µA 6
Low-level regulation threshold VTHPGD_LO -80 -35 0 mV 6
High-level regulation threshold VTHPGD_HI -165 -100 -40 mV 6
SR turn-on re-arming threshold VTHARM 1.4 1.5 1.7 V 6
Bias current on VD1 or VD2 IVDBIAS -10 0 0.5 µA VVD1 = VVD2 = -150 mV 6
VG pull-up resistance RVG_PU 3.5 6.5 11.25 Ω 6
VG pull-down resistance RVG_PD 0.2 0.9 1.5 Ω 6
VG high clamp level VGHI 9.95 10.9 11.68 V IVG = 0 mA 6
VG output low voltage, VDD low bias VGUV 1 20 100 mV VVDD = 4 V, IVG = 25 mA 6
VG output low voltage VGLO 5 100 175 mV VVDD = 12 V, IVG = 100 mA 6
VG maximum source current IVGSOURCE 0.9 1.5 2.4 A 6
VG maximum sink current IVGSINK 2.6 4 6.7 A 6
REG pin regulation level VREG 9.9 11 11.9 V VVDD = 15 V, ILOAD_REG = 0 mA 6
Load regulation on REG VREGLG 9 25 75 mV VVDD = 15 V, ILOAD_REG = 0 mA to 30 mA 6
REG drop out on passthrough mode VREGDO 0.1 0.28 0.5 V VVDD = 5 V, ILOAD_REG = 0 mA to 10 mA 6
REG short circuit current IREGSC 4.5 9.5 13 mA VVDD = 12 V, VREG = 0 V 6
REG current limit IREGLIM 41 60 95 mA VVDD = 12 V, VREG = 8 V 6
SR turn-on propagation delay, both channels tdVGON 110 155 225 ns VVD1, VVD2 moves from 4.7 V to -0.5 V in 5 ns 7
SR turn-off propagation delay, both channels tdVGOFF 5.5 23 40 ns VVD1, VVD2 moves from -0.5 V to 4.7 V in 5 ns 7
VVG1, VVG2 rise time trVG 13 23 40 ns 10% to 90%, VVDD = 12 V, CVG = 6.8 nF 7
VVG1, VVG2 fall time tfVG 19 35 ns 90% to 10%, VVDD = 12 V, CVG = 6.8 nF 7
On-time blanking tONMIN 325 475 625 ns 7
Minimum gate pullup time tMGPU 180 275 370 ns IVG1, IVG2 = 1.5 A 7
Off-time blanking tOFFMIN 440 650 855 ns 7
Standby mode detection time tSTBY_DET 5.5 7.5 10 ms 7
Average frequency entering standby mode fSLEEP 6.55 9 12.2 kHz 7
Average frequency coming out of standby mode fWAKE 11.5 15.6 21 kHz 7
Junction-to-ambient thermal resistance RθJA 108.4 °C/W 5
Junction-to-case (top) thermal resistance RθJC(top) 43.5 °C/W 5
Junction-to-board thermal resistance RθJB 53.6 °C/W 5
Junction-to-top characterization parameter ΨJT 4.9 °C/W 5
Junction-to-board characterization parameter ΨJB 52.8 °C/W 5

CAD (KiCad official)

  • Symbol: UCC24624DR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ucc24624dr-etched.step / ucc24624dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc24624dr.step / ucc24624dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (38 pp, sha256 cb5bd27d66fa0a05, retrieved 2026-10-17, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF