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UCC24612-2DBVT

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Texas Instruments Monitors & Reset Circuits, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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UCC24612-2DBVT

Texas Instruments · Monitors & Reset Circuits · SOT-23-5

UCC24612-2DBVT from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VG output Gate drive output for the controlled MOSFET, connected through a small series resistor; >1-A peak source and >4-A peak sink current, and avoid a resistor below 50 kΩ between VG and VS.
2 VS power_in Internal ground reference of the device, also used to sense the voltage drop across the SR MOSFET; avoid sharing its trace with the power path.
3 REG power_out Device bias pin from an internal linear regulator from VDD generating a regulated 9.5 V, with a recommended 2.2-µF bypass capacitor to VS (absolute maximum 12 V).
4 VDD power_in Internal linear regulator input, connected to the output voltage in low-side SR configuration or to an R-C-D bias circuit from the SR MOSFET drain in high-side configuration (absolute maximum 30 V).
5 VD input MOSFET drain voltage sensing input connected to the SR MOSFET drain pin, with an absolute maximum of 230 V and a layout that avoids sharing its trace with the power path.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Supply Chip
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD input voltage VDD -0.3 30 V 3
VD input voltage VD -0.7 230 V 3
VG input voltage VG -0.3 V max is VREG 3
VD input voltage for IVD ≤ -10 mA VD -1 230 V IVD ≤ -10 mA 3
REG input voltage REG 12 V 3
Peak VG output current -4 4 A pulsed, tPULSE ≤ 4 ms, duty cycle ≤ 1% 3
Operating junction temperature TJ -40 125 °C 3
Storage temperature Tstg -65 150 °C 3
VDD input voltage VVDD 4 28 V 5
VDD bypass capacitor CVDD 1 µF 5
REG bypass capacitor CREG 1.5 2.2 µF 5
Junction temperature TJ -40 125 °C 5
Maximum switching frequency UCC24612-2 fS_MAX 625 800 kHz UCC24612-2 5
VDD current, REG undervoltage IVDDSTART 50 105 150 μA VDD = 4 V, VD = 0 V 6
VDD current, run IVDDRUN 0.5 0.92 1.5 mA VDD = 12 V 6
VDD current, run IVDDRUN 0.5 0.9 1.5 mA VDD = 5 V 6
VDD current, standby mode IVDDSTBY 200 390 650 μA VDD = 12 V, VD = 1 V 6
VDD current, standby mode IVDDSTBY 200 320 500 μA VDD = 5 V, VD = 1 V 6
REG turn-on threshold VREGON 4.15 4.5 4.87 V Turn-on detected by IVDD rising 6
REG turn-off threshold VREGOFF 3.65 4 4.25 V Turn-off detected by IVDD falling 6
UVLO hysteresis VREGHYST 0.425 0.5 0.575 V VREGHYST = VREGON, VREGOFF 6
VG turn-on threshold VTHVGON -300 -240 -175 mV VD falling, TJ = 25°C 6
VG turn-off threshold VTHVGOFF -20 -9 -2 mV VD rising, TJ = 25°C 6
VG turn-off threshold VTHVGOFF -30 -9 -2 mV VD rising, -40°C ≤TJ ≤ 125°C 6
VG re-arming threshold VTHARM 0.4 0.5 0.6 V VD rising 6
VD pin bias current when VG is high IVDBIAS_ON -1 0 1 µA VVD = -50 mV, VVG = VGH 6
VD pin bias current when VG is low IVDBIAS_OFF -6 -2 µA VVD = -150 mV, VVG = VGL, TJ = 25°C 6
VD pin bias current when VG is low IVDBIAS_OFF -10 µA VVD = -150 mV, VVG = VGL, -40°C ≤TJ ≤ 125°C 6
VD pin leakage current IVDLK 0.06 2 µA VVD = 200 V 6
VG pull-up resistance RSOURCE 5.7 10 Ω IVG = -20 mA 6
VG pull-down resistance RSINK 0.45 1 Ω IVG = 100 mA 6
VG clamp level VGH 8.55 9.4 10.26 V 6
VG output low voltage VGL 60 150 mV IVG = 100 mA, VDD = 12 V 6
VG output low voltage in UVLO VOLGUV 0.7 V IVG = 25 mA, VDD = 4 V 6
REG pin regulation level VREG 8.55 9.4 10.26 V ILOAD_REG = 0 mA 6
Load regulation on REG VREGLG 0.016 0.1 V ILOAD_REG= 10 mA to 0 mA 6
REG drop-out on pass-through mode VREGDO 0.28 0.45 V VDD = 5 V, ILOAD_REG= 10 mA 6
REG short-circuit current IREGSC 1 5.2 15 mA VREG = 0 V 6
REG current limit IREGLIM 25 42 62 mA VREG = 8 V 6
Gate turn-on propagation delay tdVGON 120 170 225 ns VD transitions from 4.7 V to -0.3 V in 5 ns, UCC24612-2, TJ = 25°C 7
Gate turn-off propagation delay tdVGOFF 16 35 ns VD moves from -0.3 V to 4.7 V in 5 ns 7
Minimum SR conduction time tON(min) 350 540 670 ns UCC24612 -2 7
Absolute minimum SR off-time tOFF_ABSMIN 160 360 545 ns UCC24612-2 7
Maximum SR off-blanking time tOFF_MAX 2.65 3.68 4.65 µs 7
VG rise time tr_VG 10 32 65 ns 10% to 90%, CVG = 6.8 nF 7
VG fall time tf_VG 5 16 35 ns 90% to 10%, CVG = 6.8 nF 7
Standby mode detection time tSTBY_DET 3 4.5 6 ms 7
Average frequency entering standby mode fSLEEP 8 12 16 kHz 7
Average frequency coming out of standby mode fWAKE 10 15 20 kHz 7
Average frequency hysteresis for standby mode fSTB_HYS 2 3 4 kHz 7
Thermal shut-down threshold TTSD 130 165 ºC min specified by design 7
Thermal shut-down recovery hysteresis THYS 15 ºC 7
ESD HBM, all pins except pin 5 V(ESD) -2000 2000 V HBM per ANSI/ESDA/JEDEC JS-001 4
ESD HBM, pin 5 V(ESD) -1500 1500 V HBM per ANSI/ESDA/JEDEC JS-001, pin 5 4
ESD CDM, all pins V(ESD) -500 500 V CDM per JESD22-C101 4
Junction-to-ambient thermal resistance RθJA 206.6 °C/W DBV (SOT23-5) 5
Junction-to-case (top) thermal resistance RθJC(top) 97.6 °C/W DBV (SOT23-5) 5
Junction-to-board thermal resistance RθJB 44.2 °C/W DBV (SOT23-5) 5

CAD (KiCad official)

  • Symbol: UCC24612-2DBVT
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: ucc24612-2dbvt-etched.step / ucc24612-2dbvt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc24612-2dbvt.step / ucc24612-2dbvt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (38 pp, sha256 d5838705734af89c, retrieved 2026-10-24, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF