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UCC21756QDWRQ1

Public Made by Adom

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Texas Instruments Isolators - Gate Drivers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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UCC21756QDWRQ1

Texas Instruments · Isolators - Gate Drivers · SOIC-16

UCC21756QDWRQ1 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AIN input Isolated analog sensing input referenced to COM; a small capacitor to COM is recommended for noise immunity, and AIN is rated -0.3 V to 5 V with respect to COM. Tie to COM if unused.
2 DESAT input Desaturation current protection input, rated from COM-0.3 V to VDD+0.3 V; tie to COM if unused.
3 COM power_in Common ground reference for the output side, connected to the emitter of an IGBT or the source of a SiC MOSFET.
4 OUTH output Gate driver pullup output; DC voltage limited to VEE-0.3 V to VDD.
5 VDD power_in Positive gate drive supply, specified at 13 V to 33 V (VDD-COM); bypass with a >10-µF capacitor to COM placed close to the pin.
6 OUTL output Gate driver pulldown output.
7 CLMPI input Internal active Miller clamp connection, to be connected directly to the power transistor gate; leave floating or tie to VEE if unused.
8 VEE power_in Negative gate drive supply, specified at -16 V to 0 V (VEE-COM); bypass with a >10-µF capacitor to COM placed close to the pin.
9 GND power_in Input-side power supply and logic ground reference for VCC (3 V to 5.5 V).
10 IN+ input Non-inverting gate driver control input referenced to GND, with high-level input at 0.7×VCC minimum and low-level input at 0.3×VCC maximum; tie to VCC if unused.
11 IN- input Inverting gate driver control input referenced to GND; tie to GND if unused.
12 RDY output Open-drain power-good output for VCC-GND and VDD-COM that can be paralleled with other RDY signals.
13 FLT output Active-low open-drain fault alarm output asserted on overcurrent or short circuit, which can be paralleled with other fault outputs.
14 RST/EN input Enables or shuts down the output side (low turns the FET off by a regular turn-off) and resets a DESAT fault on FLT when held low for more than 1000 ns; tie to IN+ for automatic reset.
15 VCC power_in Input-side power supply rated 3 V to 5.5 V; bypass with a >1-µF capacitor to GND placed close to the pin.
16 APWM output Isolated analog sensing PWM output; leave floating if unused.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Power Management (PMIC)
Pins 16

CAD (KiCad official)

  • Symbol: UCC21756QDWRQ1
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: ucc21756qdwrq1-etched.step / ucc21756qdwrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc21756qdwrq1.step / ucc21756qdwrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (53 pp, sha256 19fdd0044cb4f6e6, retrieved 2026-10-10, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF