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UCC21750QDWQ1

Public Made by Adom

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Texas Instruments Gate Drive ICs, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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UCC21750QDWQ1

Texas Instruments · Gate Drive ICs · SOIC-16-300mil

UCC21750QDWQ1 from Texas Instruments, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AIN input Isolated analog sensing input (0.6 V to 4.5 V referenced to COM recommended); parallel a small capacitor to COM for better noise immunity and tie to COM if unused.
2 DESAT input Desaturation current protection input; tie to COM if unused.
3 COM power_in Common ground reference on the output side, connected to the emitter pin for an IGBT or the source pin for a SiC MOSFET.
4 OUTH output Gate driver output pull-up.
5 VDD power_in Positive supply rail for gate drive voltage (13 V to 33 V referenced to COM); bypass with a >10-µF capacitor to COM placed close to the pin.
6 OUTL output Gate driver output pull-down.
7 CLMPI input Internal active Miller clamp input, connected directly to the gate of the power transistor; leave floating or tie to VEE if unused.
8 VEE power_in Negative supply rail for gate drive voltage; bypass with a >10-µF capacitor to COM placed close to the pin.
9 GND power_in Input power supply and logic ground reference.
10 IN+ input Non-inverting gate driver control input; tie to VCC if unused.
11 IN- input Inverting gate driver control input; tie to GND if unused.
12 RDY output Open-drain power-good output for VCC-GND and VDD-COM that can be paralleled with other RDY signals.
13 FLT output Active-low open-drain fault alarm output upon over current or short circuit that can be paralleled with other faults.
14 RST/EN input Enable/shutdown of the output side (low causes regular turn-off) and resets the DESAT fault on FLT when held low for more than 1000 ns, with FLT reset at the rising edge.
15 VCC power_in Input power supply from 3 V to 5.5 V; bypass with a >1-µF capacitor to GND placed close to the pin.
16 APWM output Isolated analog sensing PWM output; leave floating if unused.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16-300mil
Category Power Supply Chip
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC supply voltage VCC -0.3 6 V VCC, GND 6
VDD supply voltage VDD -0.3 36 V VDD, COM 6
VEE supply voltage VEE -17.5 0.3 V VEE, COM 6
Max output supply VMAX -0.3 36 V VDD, VEE 6
Junction temperature range (abs max) TJ -40 150 °C 6
Storage temperature Tstg -65 150 °C 6
FLT/RDY pin input current IFLT, IRDY 20 mA 6
APWM output current IAPWM 20 mA 6
HBM ESD V(ESD) -4000 4000 V HBM per AEC Q100-002 6
CDM ESD V(ESD) -1500 1500 V CDM per AEC Q100-011 6
VCC supply voltage (operating) VCC 3 5.5 V VCC-GND 6
VDD supply voltage (operating) VDD 13 33 V VDD-COM 6
Max output supply (operating) VMAX 33 V VDD-VEE 6
Input high level voltage 0.7 1 V IN+, IN-, RST/EN; 0.7×VCC to VCC (factors of VCC) 6
Input low level voltage 0 0.3 V IN+, IN-, RST/EN; 0 to 0.3×VCC (factor of VCC) 6
AIN voltage AIN 0.6 4.5 V Reference to COM 6
Minimum RST/EN fault reset pulse width tRST/EN 800 ns 6
Ambient temperature TA -40 125 °C 6
Junction temperature TJ -40 150 °C 6
Junction-to-ambient thermal resistance RθJA 68.3 °C/W DW (SOIC) 16 pins 7
Junction-to-case (top) thermal resistance RθJC(top) 27.5 °C/W 7
Junction-to-board thermal resistance RθJB 32.9 °C/W 7
VCC UVLO rising threshold VVCC_ON 2.55 2.7 2.85 V VCC-GND 9
VCC UVLO falling threshold VVCC_OFF 2.35 2.5 2.65 V 9
VCC UVLO on delay to output high tVCC+ to OUT 28 37.8 50 µs IN+ = VCC, IN- = GND 9
VCC UVLO off delay to output low tVCC- to OUT 5 10 15 µs IN+ = VCC, IN- = GND 9
VCC UVLO on delay to RDY high tVCC+ to RDY 30 37.8 50 µs RST/EN = VCC 9
VCC UVLO off delay to RDY low tVCC- to RDY 5 10 15 µs RST/EN = VCC 9
VDD UVLO rising threshold VVDD_ON 10.5 12 12.8 V VDD-COM 9
VDD UVLO falling threshold VVDD_OFF 9.9 10.7 11.8 V 9
VDD UVLO on delay to output high tVDD+ to OUT 2 5 8 µs IN+ = VCC, IN- = GND 9
VDD UVLO off delay to output low tVDD- to OUT 5 10 µs IN+ = VCC, IN- = GND 9
VDD UVLO on delay to RDY high tVDD+ to RDY 10 15 µs RST/EN = FLT=High 9
VDD UVLO off delay to RDY low tVDD- to RDY 10 15 µs RST/EN = FLT=High 9
VCC quiescent current, OUT high IVCCQ 2.5 3 4 mA OUT(H) = High, fS = 0Hz, AIN = 2 V 9
VCC quiescent current, OUT low IVCCQ 1.45 2 2.75 mA OUT(L) = Low, fS = 0Hz, AIN = 2 V 9
VDD quiescent current, OUT high IVDDQ 3.6 4 5.9 mA OUT(H) = High, fS = 0Hz, AIN = 2 V 9
VDD quiescent current, OUT low IVDDQ 3.1 3.7 5.3 mA OUT(L) = Low, fS = 0Hz, AIN = 2 V 9
Input high threshold VINH 1.85 2.31 V VCC = 3.3 V 9
Input low threshold VINL 0.99 1.52 V VCC = 3.3 V 9
Input threshold hysteresis VINHYS 0.33 V VCC = 3.3 V 9
Input high level leakage current IIH 90 µA VIN = VCC 9
Input low level leakage current IIL -90 µA VIN = GND 9
Input pull-down resistance RIND 55 kΩ see Detailed Description 9
Input pull-up resistance RINU 55 kΩ see Detailed Description 9
Input deglitch filter time TINFIL 28 40 60 ns fS = 50 kHz 9
Deglitch filter time to reset FLT TRSTFIL 400 650 800 ns 9
Peak source current IOUTH 10 A CL = 0.18 µF, fS = 1 kHz 9
Peak sink current IOUTL 10 A CL = 0.18 µF, fS = 1 kHz 9
Output pull-up resistance ROUTH 2.5 Ω IOUT = -0.1 A 9
Output pull-down resistance ROUTL 0.3 Ω IOUT = 0.1 A 9
Output active pull down voltage VOUTPD 1.5 2 2.5 V IOUTL or IOUT = 0.1 × IOUT(L)(tpy), VDD=OPEN, VEE=COM 9
Miller clamp threshold voltage VCLMPTH 1.5 2 2.5 V Reference to VEE 9
DESAT detection threshold VDESAT 8.5 9.15 9.8 V 10
Blanking capacitor charge current ICHG 430 500 570 µA VDESAT = 2.0 V 10
DESAT deglitch filter tDESATFIL 50 140 230 ns 10
DESAT propagation delay to OUT(L) 90% tDESATOFF 150 200 300 ns 10
DESAT to FLT low delay tDESATFLT 400 580 750 ns 10
Soft turn-off current ISTO 250 400 570 mA VDD-VEE=20V, VOUTL-COM=8V 10
Internal current source IAIN 196 200 209 µA VAIN = 2.5 V, -40°C < TJ< 150°C 10
APWM output frequency fAPWM 380 400 420 kHz VAIN = 2.5 V 10
Propagation delay High to Low tPDHL 60 90 130 ns 11
Propagation delay Low to High tPDLH 60 90 130 ns 11

CAD (KiCad official)

  • Symbol: UCC21750QDWQ1
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: ucc21750qdwq1-etched.step / ucc21750qdwq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc21750qdwq1.step / ucc21750qdwq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (57 pp, sha256 0bce5c031890cf7b, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF