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UCC21550ADWR

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Texas Instruments Isolators - Gate Drivers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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UCC21550ADWR

Texas Instruments · Isolators - Gate Drivers · SOIC-16

UCC21550ADWR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 INA input Input signal for A channel with TTL/CMOS compatible threshold, pulled low internally if left open; an RC filter of R = 10 Ω to 100 Ω and C = 10 pF to 100 pF is recommended.
2 INB input Input signal for B channel with TTL/CMOS compatible threshold, pulled low internally if left open; an RC filter of R = 10 Ω to 100 Ω and C = 10 pF to 100 pF is recommended.
3 VCCI power_in Primary-side supply voltage, to be locally decoupled to GND with a low ESR/ESL capacitor placed as close to the device as possible.
4 GND power_in Primary-side ground reference to which all primary-side signals are referenced.
5 DIS input Disables both driver outputs when high and enables both when low; tie to ground if unused, internally pulled high if floating, with a recommended RC filter of R = 0 Ω to 100 Ω and C = 100 pF to 1000 pF.
6 DT input Dead time programming: float or short to VCCI disables the interlock, a 1.7-kΩ to 100-kΩ resistor to GND sets the minimum dead time, and 0 Ω to 150 Ω or a short to GND interlocks the outputs; do not bypass with a ceramic capacitor >1nF.
7 NC unconnected No internal connection.
8 VCCI power_in Primary-side supply voltage, internally shorted to pin 3.
9 VSSB power_in Ground reference for secondary side B channel.
10 OUTB output Output of driver B, connected to the gate of the B channel transistor through a gate resistor.
11 VDDB power_in Secondary-side power for driver B, to be locally decoupled to VSSB with a low ESR/ESL capacitor placed as close to the device as possible.
12 NC unconnected No internal connection.
13 NC unconnected No internal connection.
14 VSSA power_in Ground reference for secondary side A channel.
15 OUTA output Output of driver A, connected to the gate of the A channel transistor through a gate resistor.
16 VDDA power_in Secondary-side power for driver A, to be locally decoupled to VSSA with a low ESR/ESL capacitor placed as close to the device as possible.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Power Management (PMIC)
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input bias supply voltage VCCI -0.3 6 V VCCI to GND 5
Output bias supply voltage VDDA, VDDB -0.3 30 V VDDA, VDDB to VSS 5
Input signal DC voltage INA, INB, DT, DIS -0.3 6 V to GND; max printed as VCCI + 0.3, must not exceed 6 V 5
Junction temperature TJ -40 150 °C 5
Storage temperature Tstg -65 150 °C 5
ESD HBM V(ESD) -2000 2000 V Human body model, all pins 5
ESD CDM V(ESD) -1000 1000 V Charged device model, all pins 5
Input bias pin supply voltage VCCI 3 5.5 V 5
Output bias supply voltage VDDA, VDDB 6.5 25 V UCC21550A - 5V UVLO, VDDA-VSSA, VDDB-VSSB 5
Junction temperature TJ -40 150 °C 5
Junction-to-ambient thermal resistance RθJA 69.8 °C/W DW 16 pins 5
Junction-to-case (top) thermal resistance RθJC(top) 33.1 °C/W DW 16 pins 5
Junction-to-board thermal resistance RθJB 36.9 °C/W DW 16 pins 5
Junction-to-top characterization parameter ΨJT 22.2 °C/W DW 16 pins 5
Junction-to-board characterization parameter ΨJB 36 °C/W DW 16 pins 6
Maximum power dissipation (both sides) PD 950 mW VCCI = 5V, VDDA/VDDB = 20V, INA/B = 3.3V, 460kHz 50% duty cycle square wave, CL=2.2nF, TJ=150℃, TA=25℃ 6
Maximum power dissipation by transmitter side PDI 50 mW 6
Maximum power dissipation by each driver side PDA, PDB 450 mW 6
VCC quiescent current IVCC 1.4 2 mA VINx = 0 V, DIS = GND; VCC=3.3V (same for VCC=5V) 9
VCC quiescent current IVCC 4.2 4.8 mA VINx = VCC, DIS = GND; VCC=3.3V (same for VCC=5V) 9
VCC quiescent current IVCC 2.7 3.2 mA VINx PWM at 0V to VCC at fSW = 500kHz, DIS = GND; VCC=3.3V (same for VCC=5V) 9
VDDx quiescent current IVDDx 1.2 2 mA VINx = 0 V, DIS = GND 9
VDDx quiescent current IVDDx 1.4 2.3 mA VINx = 0 V, DIS = GND; VDD=25V 9
VDDx quiescent current IVDDx 1.4 2.2 mA VINx = VCC, DIS = GND 9
VDDx quiescent current IVDDx 1.5 2.5 mA VINx = VCC, DIS = GND; VDD=25V 9
VDDx quiescent current IVDDx 2.7 4.4 mA VINx PWM at 0V to VCC at fSW = 500kHz, DIS = GND (same for VDD=25V) 9
VCC UVLO Rising Threshold VVCC_ON 2.55 2.7 2.85 V 9
VCC UVLO Falling Threshold VVCC_OFF 2.35 2.5 2.65 V 9
VCC UVLO Threshold Hysteresis VVCC_HYS 0.2 V 9
VCC UVLO ON Delay tVCC+ to OUT 18 42 80 µs 9
VCC UVLO OFF Delay tVCC- to OUT 0.5 1.2 7 µs 9
VCC UVLO Deglitch Filter tVCCFIL 0.4 0.9 3.1 µs 9
VDDx UVLO Rising Threshold VVDD_ON 5.7 6 6.3 V 5-V UVLO Option 9
VDDx UVLO Falling Threshold VVDD_OFF 5.4 5.7 6 V 5-V UVLO Option 9
VDDx UVLO Threshold Hysteresis VVDD_HYS 0.3 V 5-V UVLO Option 9
VDDx UVLO ON Delay tVDD+ to OUT 10 µs 9
VDDx UVLO OFF Delay tVDD- to OUT 0.1 0.5 2 µs 9
Input High Threshold Voltage VINx_H, VDIS_H 2 2.3 V 9
Input Low Threshold Voltage VINx_L, VDIS_L 0.8 1 V 9
Input Threshold Hysteresis VINx_HYS, VDIS_HYS 1 V 9
INx Pin Pull Down Resistance RINxD 50 90 185 kΩ INx = 3.3V 9
DIS Pin Pull Up Resistance RDISD 50 90 185 kΩ DIS= 3.3V 9
Peak Output Source Current IO+ -4 A CVDDx = 10 µF, CL = 0.22 µF, f = 1 kHz 9
Peak Output Sink Current IO- 6 A CVDDx = 10 µF, CL = 0.22 µF, f = 1 kHz 9
Pull up resistance ROH 5 Ω IOUTx = -0.05A 10
Pull down resistance ROL 0.55 Ω IOUTx = 0.05A 10
Output Active Pull Down on OUTx VOUTPD 1.6 2 V IOUT = 200mA, VDDx floating and unpowered. 10
Dead time, RDT≤0.15kΩ DTS -6 0.2 6 ns RDT=0~0.15kΩ 10
Dead time RDT = 10 kΩ DT 86 99 112 ns RDT = 10 kΩ 10
Dead time RDT = 20 kΩ DT 167 185 203 ns RDT = 20 kΩ 10
Dead time RDT = 50 kΩ DT 399 443 487 ns RDT = 50 kΩ 10
Output Rise Time tRISE 8 ns CL=1.8nF, VDDx=12V, 20% to 80% 10
Output Fall Time tFALL 8 ns CL=1.8nF, VDDx=12V, 10% to 90% 10
Propagation Delay, Low to High tPDLH 26 33 45 ns Input Pulse Width = 100ns, 500kHz, measure with Input VIH to output 10% 10
Propagation Delay, High to Low tPDHL 26 33 45 ns Input Pulse Width = 100ns, 500kHz, measure with Input VIL to output 90% 10
DIS Response Delay, High to Low tPD_DIS_HL 27 48 80 ns tEN/DIS_FIL = 20 ns (typ), VDD=VDD_ON+0.2V and above, Input Pulse Width = 100ns, 500kHz 10
Minimum Input Pulse Width That Passes to Output tPWmin 4 12 30 ns VDD=VDD_ON+0.2V and above 10
Propagation Delay Matching tDM 0 5 ns Input Pulse Width = 100ns, 500kHz, TJ = -10°C to +150°C 10
Pulse Width Distortion tPWD 0 5 ns Input Pulse Width = 100ns, 500kHz 10
High-level Common Mode Transient Immunity /CMH/ 125 V/ns VCM = 1500V 10

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper • Increasing the PCB copper connecting to VDDA, VDDB, VSSA and VSSB pins is recommended, with priority 39

CAD (KiCad official)

  • Symbol: UCC21550ADWR
  • Footprint: Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: ucc21550adwr-etched.step / ucc21550adwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc21550adwr.step / ucc21550adwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (54 pp, sha256 5f80a86ae72418d7, retrieved 2026-10-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF