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docs ucc21220adr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
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package.json ucc21220adr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
page.json ucc21220adr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
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ucc21220adr-etched.fit.json ucc21220adr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ucc21220adr-etched.glb ucc21220adr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ucc21220adr-etched.step ucc21220adr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
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UCC21220ADR

Texas Instruments · Isolators - Gate Drivers · SOIC-16

UCC21220ADR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 INA input Input signal for channel A with TTL/CMOS compatible threshold; internally pulled low if left open.
2 INB input Input signal for channel B with TTL/CMOS compatible threshold; internally pulled low if left open.
3 VCCI power_in Primary-side input supply voltage, 3 to 5.5 V range; must be locally decoupled to GND with low ESR/ESL capacitor.
4 GND power_in Primary-side ground reference for all primary-side signals.
5 DIS input Disable input; pull high or leave open to disable both outputs, ground to enable; internally pulled high if left open.
6 NC unconnected No internal connection.
7 NC unconnected No internal connection.
8 VCCI power_in Primary-side input supply voltage, internally shorted to pin 3.
9 VSSB power_in Secondary-side ground reference for channel B driver.
10 OUTB output Channel B driver output, sources 4 A peak and sinks 6 A peak; connect to FET or IGBT gate.
11 VDDB power_in Secondary-side power for driver B, 6.5 to 25 V range for 5V UVLO version; must be locally decoupled to VSSB with low ESR/ESL capacitor.
12 NC unconnected No internal connection.
13 NC unconnected No internal connection.
14 VSSA power_in Secondary-side ground reference for channel A driver.
15 OUTA output Channel A driver output, sources 4 A peak and sinks 6 A peak; connect to FET or IGBT gate.
16 VDDA power_in Secondary-side power for driver A, 6.5 to 25 V range for 5V UVLO version; must be locally decoupled to VSSA with low ESR/ESL capacitor.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Power Management (PMIC)
Pins 16

CAD (KiCad official)

  • Symbol: UCC21220ADR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: ucc21220adr-etched.step / ucc21220adr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc21220adr.step / ucc21220adr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (45 pp, sha256 71440c65170dc667, retrieved 2026-09-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF